IP Library Granted Patent US 8,207,042
Granted Patent B2
US 8,207,042 · App. 12/564,313 · Granted Jun 26, 2012

Semiconductor device and method of manufacturing the same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,207,042
App. No.
12/564,313
Granted
Jun 26, 2012
Kind
B2
Abstract

A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.

Claims (60)

1. A method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a silicon substrate;

forming a gate electrode on the gate insulating film;

forming two first conductivity type impurity diffused layers in the silicon substrate using the gate electrode as a mask;

forming a trench in each of the impurity diffused layers; and

epitaxially growing a first conductivity type semiconductor layer from a bottom of the trench, wherein

a conductivity type of a region of the silicon substrate immediately below the gate insulating film is a second conductivity type, and

said epitaxially growing the semiconductor layer comprises:

forming a first region including a portion located within or lower than a same plane with an interface between the silicon substrate and the gate insulating film; and

forming a second region closer to a bottom side of the trench than the first region before forming the first region, the second region having a lattice constant closer to a lattice constant of silicon than a lattice constant of the first region.

2. A method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a silicon substrate;

forming a gate electrode on the gate insulating film;

forming two trenches in the silicon substrate using the gate electrode as a mask;

epitaxially growing a first conductivity type semiconductor layer from a bottom of each of the two trenches; and

forming a first conductivity type impurity diffused layer in the silicon substrate and the first conductivity type semiconductor layer;

wherein a conductivity type of a region of the silicon substrate immediately below the gate insulating film is a second conductivity type, and

said epitaxially growing the semiconductor layer comprises:

forming a first region including a portion located within or lower than a same plane with an interface between the silicon substrate and the gate insulating film; and

forming a second region closer to a bottom side of the trench than the first region before forming the first region, the second region having a lattice constant closer to a lattice constant of silicon than a lattice constant of the first region.

3. The method of manufacturing a semiconductor device according to claim 1 , wherein

the second region is constituted of silicon germanium having a germanium concentration which increases with distance from the bottom of the trench, and

the first region is constituted of silicon germanium having a germanium concentration that corresponds to the germanium concentration at an uppermost portion of the second region.

4. The method of manufacturing a semiconductor device according to claim 3 , wherein

a germanium concentration in the first region is 20 atom % or higher, and

a germanium concentration in the second region is lower than 20 atom %.

5. The method of manufacturing a semiconductor device according to claim 1 , wherein

said epitaxially growing the semiconductor layer comprises forming a third region having a lattice constant closer to the lattice constant of silicon than the lattice constant of the first region above the first region, and

the method further comprising forming a silicide layer on the third region.

6. The method of manufacturing a semiconductor device according to claim 5 , wherein as the third region, a region constituted of silicon or a region constituted of silicon germanium having a germanium concentration lower than 20 atom % is formed.

7. The method of manufacturing a semiconductor device according to claim 5 , wherein said forming the third region comprises:

epitaxially growing a lower region at a first temperature; and

epitaxially growing an upper region on the lower region at a second temperature higher than the first temperature.

8. A method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a silicon substrate;

forming a gate electrode on the gate insulating film;

forming two first conductivity type impurity diffused layers in the silicon substrate using the gate electrode as a mask;

forming a trench in each of the impurity diffused layers;

epitaxially growing a first conductivity type semiconductor layer from a bottom of the trench; and

forming a silicide layer on the semiconductor layer, wherein

a conductivity type of a region of the silicon substrate immediately below the gate insulating film is a second conductivity type, and

said epitaxially growing the semiconductor layer comprises:

forming a fourth region including a portion located within or lower than a same plane with an interface between the silicon substrate and the gate insulating film; and

forming a fifth region in contact with the silicide layer, the fifth region having a lattice constant closer to a lattice constant of silicon than a lattice constant of the fourth region.

9. A method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a silicon substrate;

forming a gate electrode on the gate insulating film;

forming two trenches in the silicon substrate using the gate electrode as a mask;

epitaxially growing a first conductivity type semiconductor layer from a bottom of each of the two trenches; and

forming a first conductivity type impurity diffused layer in the silicon substrate and the first conductivity type semiconductor layer, wherein

a conductivity type of a region of the silicon substrate immediately below the gate insulating film is a second conductivity type, and

said epitaxially growing the semiconductor layer comprises:

forming a fourth region including a portion located within or lower than a same plane with an interface between the silicon substrate and the gate insulating film; and

forming a fifth region in contact with the silicide layer, the fifth region having a lattice constant closer to a lattice constant of silicon than a lattice constant of the fourth region.

10. The method of manufacturing a semiconductor device according to claim 8 , wherein

the fourth region is constituted of silicon germanium having a germanium concentration of 20 atom % or higher, and

as the fifth region, a region constituted of silicon or a region constituted of silicon germanium having a germanium concentration lower than 20 atom % is formed.

11. The method of manufacturing a semiconductor device according to claim 8 , wherein said forming the fifth region comprises:

epitaxially growing a lower region at a first temperature; and

epitaxially growing an upper region on the lower region at a second temperature higher than the first temperature.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →