Method and fabricating semiconductor device and semiconductor device
A method for fabricating a semiconductor device includes the steps of: forming a plurality of lower interconnections at intervals in a first insulating film; removing a portion of the first insulating film located between the lower interconnections, thereby forming an interconnection-to-interconnection gap; forming a second insulating film over the first insulating film in which the lower interconnections and the interconnection-to-interconnection gap are formed such that an air gap is formed out of the interconnection-to-interconnection gap; and forming, in the second insulating film, a connection portion connected to one of the lower interconnections and an upper interconnection connected to the connection portion. The connection portion is formed to be connected to one of the lower interconnections not adjacent to the air gap.
1. A method for fabricating a semiconductor device, the method comprising the steps of:
forming a plurality of lower interconnections at intervals in a first insulating film;
removing a portion of the first insulating film located between the lower interconnections, thereby forming an interconnection-to-interconnection gap;
forming a second insulating film over the first insulating film in which the lower interconnections and the interconnection-to-interconnection gap are formed such that an air gap is formed out of the interconnection-to-interconnection gap; and
forming, in the second insulating film, a connection portion connected to one of the lower interconnections and an upper interconnection connected to the connection portion,
wherein the connection portion is formed to be connected to one of the lower interconnections not adjacent to the air gap.
2. The method of claim 1 , wherein
the method further comprises the step of selectively forming a cap layer on each of the surfaces of the lower interconnections, after the step of forming the lower interconnections and before the step of forming the interconnection-to-interconnection gap.
3. The method of claim 1 , wherein
the surfaces of the lower interconnections are lower than the surface of the first insulating film.
4. The method of claim 1 , wherein
an interconnection-to-interconnection space X between the lower interconnections sandwiching the air gap satisfies the following relationship:
S≦X<3S
where S is a minimum interconnection-to-interconnection space between the lower interconnections formed at a minimum resolution of lithography.
5. The method of claim 1 , wherein
the air gap is located, from the connection portion, at least at a distance y satisfying the following relationship:
y=S +( L/ 2)
where S is a minimum interconnection-to-interconnection space between the lower interconnections formed at a minimum resolution of lithography and L is a minimum interconnection width of the lower interconnections formed at the minimum resolution of lithography.
6. The method of claim 1 , wherein
the interconnection-to-interconnection gap is formed using a resist pattern as a mask, and
the resist pattern has an opening pattern for exposing a region which is located between the lower interconnections and in which the interconnection-to-interconnection gap is to be formed and a region expanded from that region toward the lower interconnections sandwiching the region by a distance z satisfying the following relationship:
z=L/ 2
where L is the minimum interconnection width of the lower interconnections formed at the minimum resolution of lithography.
7. The method of claim 1 , wherein
the method further comprises the step of planarizing the surface of the second insulating film by CMP after the step of forming the second insulating film and before the step of forming the upper interconnection and the connection portion.