IP Library Granted Patent US 7,952,509
Granted Patent B2
US 7,952,509 · App. 12/620,546 · Granted May 31, 2011

Successive approximation A/D converter

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Quick Facts
Patent No.
US 7,952,509
App. No.
12/620,546
Granted
May 31, 2011
Kind
B2
Abstract

A successive approximation A/D conversion circuit for simultaneously sampling N channels of analog signals and for A/D converting the sampled analog signals, includes: N capacitive main DACs; a resistive sub DAC; N comparators; and a successive approximation control circuit, wherein the successive approximation control circuit determines high-order bit values of A/D conversion results of the N channels of analog signals by controlling the N capacitive main DACs and the N comparators, and determines low-order bit values of the A/D conversion results of the N channels of analog signals by controlling the resistive sub DAC and the N comparators.

Claims (15)

1. A successive approximation A/D conversion circuit for simultaneously sampling N channels of analog signals and for A/D converting the sampled analog signals, comprising:

N capacitive DACs;

a resistive DAC;

N comparators; and

a successive approximation control circuit, wherein

the successive approximation control circuit determines high-order bit values of A/D conversion results of the N channels of analog signals by controlling the N capacitive DACs and the N comparators, and

determines low-order bit values of the A/D conversion results of the N channels of analog signals by controlling the resistive DAC and the N comparators.

2. The successive approximation A/D conversion circuit according to claim 1 , wherein the resistive DAC comprises:

a resistor string; and

a switch array comprising a plurality of switches each connected at one end to a connection node of the resistor string and at an opposite end to an output of the resistive DAC.

3. The successive approximation A/D conversion circuit according to claim 2 , wherein the output of the resistive DAC is connected in common to the N capacitive DACs.

4. The successive approximation A/D conversion circuit according to claim 3 , wherein

the resistive DAC comprises a plurality of the switch arrays, and

the plurality of switches in each of the switch arrays are connected at the opposite end to a corresponding one of the N capacitive DACs, and wherein

when the switch arrays are smaller in number than the number N, the plurality of switches in one or some of the switch arrays are connected in common at the opposite end to some of the N capacitive DACs.

Assignments (9)
MERGER Recorded Nov 14, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073571/0456 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036050/0337 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Sep 27, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 025046/0478 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2010
From: ARUGA, KENTA; TACHIBANA, SUGURU; OKADA, KOJI
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 023890/0796 →