Semiconductor integrated circuit device with reduced cell size
A technique permitting reduction in size of a standard cell is provided. In a semiconductor integrated circuit device comprising a first tap formed in a first direction to supply a power-supply potential, a second tap formed in the first direction to supply a power-supply potential and positioned so as to confront the first tap in a second direction intersecting the first direction, and a standard cell formed between the first and second taps, a cell height (distance) between the center of the first tap and that of the second tap both in the second direction is set to ((an integer+0.5)×a wiring pitch of the second-layer wiring lines) or [(an integer+0.25)×a wiring pitch of the second-layer wiring lines].
1. A semiconductor integrated circuit device comprising:
a first tap for the supply of a first potential, the first tap being formed in a first direction;
a second tap for the supply of a second potential, the second tap being formed in the first direction and positioned so as to confront the first tap in a second direction intersecting the first direction;
a cell array comprising a plurality of standard cells each formed between the center of the first tap in the second direction and the center of the second tap in the second direction; and
a plurality of layers of wiring lines formed over the first tap, the second tap and the cell array,
wherein a cell height between the first and second taps is set to a value equal to the product of an integer representing a number of wiring lines in the first direction and increased by 0.5, and a wiring pitch of second-layer wiring lines of the plurality of layers of wiring lines.
2. A semiconductor integrated circuit device according to claim 1 ,
wherein the integer is a number of the second-layer or higher-layer wiring lines formed in the first direction and able to pass between the first and second taps.
3. A semiconductor integrated circuit device according to claim 1 ,
wherein the first potential is a power-supply potential and the second potential is a ground potential.
4. A semiconductor integrated circuit device according to claim 1 ,
wherein the wiring pitch is a minimum wiring pitch obtained by adding together a wiring width and a wiring spacing each formed at a minimum machining size.
5. A semiconductor integrated circuit device according to claim 1 ,
wherein the interior of each of the standard cells is wired by the first-layer wiring lines out of the plural layers of wiring lines.
6. A semiconductor integrated circuit device according to claim 1 ,
wherein the cell array includes a plurality of the standard cells, the standard cells being coupled to each other by the second-layer or higher-layer wiring lines.