IP Library Granted Patent US 8,883,577
Granted Patent B2
US 8,883,577 · App. 12/639,561 · Granted Nov 11, 2014

Semiconductor device and producing method thereof

Inventor: Yasuo Nara (Tokyo, JP)
Assignee: Fujitsu Semiconductor Limited
H01L29/66545H01L21/823821H01L29/66795H01L29/785
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Quick Facts
Patent No.
US 8,883,577
App. No.
12/639,561
Granted
Nov 11, 2014
Kind
B2
Abstract

A semiconductor device manufacturing method includes forming a fin region over a substrate, forming a dummy gate electrode over the fin region, forming a first insulating film over the dummy gate electrode and the fin region, polishing the first insulating film until the dummy gate electrode is exposed, removing part of the exposed dummy gate electrode to form a trench, forming a gate insulator over the surface of the fin region exposed in the trench, and forming a gate electrode over the gate insulator.

Claims (23)

1. A semiconductor device manufacturing method comprising:

forming a fin region over a substrate, the fin region having an apex portion and a sidewall portion and extending in a first direction;

forming a dummy gate electrode over the fin region, the dummy gate electrode extending in a second direction different from the first direction;

forming a first insulating film over the dummy gate electrode and the fin region;

polishing the first insulating film until the dummy gate electrode is exposed;

removing at least part of the exposed dummy gate electrode to form a trench, a surface of the fin region being exposed in the trench while leaving at least part of the dummy gate electrode positioned under the first insulating film and a second part of the dummy gate electrode at a bottom portion of the trench without removing;

after removing the exposed dummy gate electrode, forming a gate insulator over the surface of the fin region exposed in the trench;

depositing a gate electrode material over the gate insulator and over the first insulating film; and

polishing the gate electrode material over the first insulating film until the first insulating film is exposed to form a gate electrode.

2. The semiconductor device manufacturing method according to claim 1 , further comprising:

forming an insulating cap layer before forming the dummy gate electrode, the apex portion of the fin region being covered with the insulating cap layer.

3. The semiconductor device manufacturing method according to claim 1 , further comprising:

implanting an impurity in the fin region using the dummy gate electrode as a mask to form a source/drain region.

4. The semiconductor device manufacturing method according to claim 3 , wherein forming the source/drain region comprises:

implanting a first impurity in the fin region using the dummy gate electrode as a mask;

forming a sidewall spacer in the sidewall portion of the fin region after implanting the first impurity; and

implanting a second impurity in the fin region using the dummy gate electrode and the sidewall spacer as masks.

5. The semiconductor device manufacturing method according to claim 3 , further comprising:

forming a silicide layer on a surface of the source/drain region.

6. The semiconductor device manufacturing method according to claim 1 , wherein the dummy gate electrode includes nitride silicon.

7. The semiconductor device manufacturing method according to claim 1 , wherein the gate electrode includes at least one of TiN and W.

8. The semiconductor device manufacturing method according to claim 1 , wherein the substrate is a semiconductor on insulator substrate.

9. The semiconductor device manufacturing method according to claim 1 , wherein the gate insulator is formed by laminating an oxide silicon film and an insulating film from at least one of the group consisting of a HfSiO film, a HfSiON film, a HfO 2 film, a HfAlO film, a HfAlON film, a LaO 2 film, a LaSiO film, and a LaAlO film.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2009
From: NARA, YASUO
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 023673/0445 →
Priority Claims (1)
JP 2008-331992 · Dec 26, 2008 · national
Continuity (1)
Related Publication 20100167475A1 · Jul 1, 2010