Boost operational amplifier

1. An apparatus comprising:

a differential amplifying unit configured to amplify and output an inputted differential voltage;

a first mirroring unit configured to mirror a current flowing through a first output terminal of said differential amplifying unit, said first mirroring unit configured to output a mirrored first mirror current;

a second mirroring unit configured to mirror a current flowing through a second output terminal of said differential amplifying unit, said second mirroring unit configured to output a mirrored second mirror current;

a pull-up transistor connected between a first power source and an output node, said pull-up transistor configured to switch based on said first and second mirror currents; and

a pull-down transistor connected between a second power source and said output node, said pull-down transistor configured to switch based on said first and second mirror currents,

wherein said first mirroring unit comprises:

a 1 st transistor connected between said first power source and said first output terminal including a gate and a drain connected to each other;

a 2 nd transistor connected between said first power source and a gate of said pull-up transistor, said 2 nd transistor including a gate connected to the gate of said 1 st transistor; and

a 3 rd transistor connected between said first power source and a gate of said pull-down transistor, connected to the gate of said 1 st transistor.

2. The apparatus of claim 1 , comprising a current source connected between said output node and said second power source.

3. An apparatus comprising:

a differential amplifying unit configured to amplify and output an inputted differential voltage;

a first mirroring unit configured to mirror a current flowing through a first output terminal of said differential amplifying unit, said first mirroring unit configured to output a mirrored first mirror current;

a second mirroring unit configured to mirror a current flowing through a second output terminal of said differential amplifying unit, said second mirroring unit configured to output a mirrored second mirror current;

a pull-up transistor connected between a first power source and an output node, said pull-up transistor configured to switch based on said first and second mirror currents; and

a pull-down transistor connected between a second power source and said output node, said pull-down transistor configured to switch based on said first and second mirror currents, wherein said first mirroring unit comprises:

a first current mirror connected between said first power source and said first output terminal and between said first power source and a gate of said pull-up transistor to mirror a current flowing between said first power source and said first output terminal, said first current mirror configured to provide said mirrored current to the gate of said pull-up transistor; and

a second current mirror connected between said first power source and said first output terminal and between said first power source and a gate of said pull-down transistor to mirror said current flowing between said first power source and said first output terminal, said second current mirror configured to provide said mirrored current to the gate of said pull-down transistor.

4. An apparatus comprising:

a differential amplifying unit configured to amplify and output an inputted differential voltage;

a first mirroring unit configured to mirror a current flowing through a first output terminal of said differential amplifying unit, said first mirroring unit configured to output a mirrored first mirror current;

a second mirroring unit configured to mirror a current flowing through a second output terminal of said differential amplifying unit, said second mirroring unit configured to output a mirrored second mirror current;

a pull-up transistor connected between a first power source and an output node, said pull-up transistor configured to switch based on said first and second mirror currents; and

a pull-down transistor connected between a second power source and said output node, said pull-down transistor configured to switch based on said first and second mirror currents, wherein said second mirroring unit comprises:

a third current mirror connected between said first power source and said second output terminal and between said second power source and a gate of said pull-up transistor to mirror a current flowing between said first power source and said second output terminal, said second current mirror configured to provide said mirrored current to the gate of said pull-up transistor; and

a fourth current mirror connected between said first power source and said second output terminal and between said second power source and a gate of said pull-down transistor to mirror said current flowing between said first power source and said second output terminal, said fourth current mirror providing said mirrored current to the gate of said pull-down transistor.

5. The apparatus of claim 1 , wherein said second mirroring unit comprises:

a 4 th transistor connected between said first power source and said second output terminal including a drain and a gate connected to each other;

a 5 th transistor having one end connected to said first power source, said 5 th transistor including a gate connected to the gate of said 4 th transistor;

a 6 th transistor connected between another end of said 5 th transistor and said second power source including a drain and a gate connected to each other;

a 7 th transistor connected between a gate of said pull-down transistor and said second power source, said 7 th transistor including a gate connected to the gate of said 6 th transistor; and

an 8 th transistor connected between a gate of said pull-up transistor and said second power source, said 8 th transistor including a gate connected to the gate of said 6 th transistor.

6. The apparatus of claim 5 , wherein each of said 1 st to 3 rd transistors comprises an NMOS transistor.

7. The apparatus of claim 5 , wherein each of said 4 th and 5 th transistors comprises an NMOS transistor and each of said 6 th to 8 th transistors comprises a PMOS transistor.

8. The apparatus of claim 7 , wherein said pull-up transistor comprises an NMOS transistor and said pull-down transistor comprises a PMOS transistor.

9. The apparatus of claim 1 , comprising a resistor and a capacitor connected in series between a gate of said pull-up transistor and said output node.