Method and apparatus for digitally equalizing a signal in a distributed antenna system
View Patent ↗Systems and methods for digitally equalizing a signal in a distributed antenna system are provided. In one embodiment, a signal processing device within a distributed antenna system comprises a signal path within a signal processing board, the signal path having an uncompensated distortion function of G(ω) with a system response represented by y(n); and a compensator coupled to the signal path, the compensator having a finite impulse response (FIR) filter with an impulse response function represented by H(ω), the compensator having an FIR filter parameter vector {right arrow over (h)} determined from an estimated system response y(n) of the signal path to an input comb signal x(n), wherein y(n) is estimated from interpolated measured output responses of the signal path to a plurality of frequency sweep signal test inputs.
1. A signal processing device within a distributed antenna system, the signal processing device comprising:
a signal path within a signal processing board, the signal path having an uncompensated distortion function of G(ω) with a system response represented by y(n); and
a compensator coupled to the signal path, the compensator having a finite impulse response (FIR) filter with an impulse response function represented by H(ω), the compensator having an FIR filter parameter vector {right arrow over (h)} determined from an estimated system response y(n) of the signal path to an input comb signal x(n), wherein y(n) is estimated from interpolated measured output responses of the signal path to a plurality of frequency sweep signal test inputs.
2. The signal processing device of claim 1 , wherein the FIR filter parameter vector {right arrow over (h)} is determined by a calculation based on
{right arrow over (h)} =( {right arrow over (Y)} H {right arrow over (Y)} ) −1 {right arrow over (Y)} H {right arrow over (d)}
wherein {right arrow over (Y)} is a convolution matrix representing channel.
3. The signal processing device of claim 1 , further comprising a memory, wherein coefficients for the vector {right arrow over (h)} are stored in the memory.
4. The signal processing device of claim 1 , wherein the compensator is implemented using a field programmable gate array (FPGA).
5. The signal processing device of claim 1 , wherein the signal path of the signal processing board comprises a digital-to-analog converter (DAC) and at least one frequency up-converter.
6. The signal processing device of claim 1 , wherein the signal path of the signal processing board comprises an analog-to-digital converter (ADC) and at least one frequency down-converter.
7. The signal processing device of claim 1 , further comprising a self-calibration module for calculating coefficients of the FIR filter parameter vector {right arrow over (h)} based on a test signal generated by the self-calibration module.
8. The signal processing device of claim 7 , wherein the self-calibration module estimates the system response function y(n) for the signal processing board based on the plurality of frequency sweep signal test inputs by solving for coefficients of a vector h(n) based on a difference between a vector d(n) and a convolution h(n)*y(n), wherein d(n) represents an input to the system response function y(n) subject to a delay; and
wherein the self-calibration module adjusts the finite impulse response (FIR) filter based on the coefficients of the vector h(n).
9. A method for calibrating a signal processing board, the method comprising:
setting a compensator within a first signal path of a signal processing board to have a flat response across a first pass band of the signal processing board;
applying a plurality of test signals to an input of the signal processing board, the plurality of test signals spaced in frequency across the first pass band;
determining a gain value for each of the plurality of test signals based on an output of the signal processing board;
estimating a system response function y(n) for the signal processing board based on the gain value for each of the plurality of test signals;
solving for coefficients of a vector h(n) based on a difference between a vector d(n) and a convolution h(n)*y(n), wherein d(n) represents an input to the system response function y(n) subject to a delay; and
setting coefficients of a finite impulse response (FIR) filter within the compensator based on the coefficients of the vector h(n).
10. The method of claim 9 , wherein the vector h(n) is determined such that a squared error between d(n) and the convolution h(n)*y(n) is minimized with respect to h(n).
11. The method of claim 9 , wherein the first signal path of the signal processing board comprises a digital-to-analog converter (DAC) and at least one frequency up-converter.
12. The method of claim 9 , wherein the first signal path of the signal processing board comprises an analog-to-digital converter (ADC) and at least one frequency down-converter.
13. The method of claim 9 , wherein setting coefficients of the finite impulse response (FIR) filter within the compensator based on the coefficients of the vector h(n) further comprises storing the coefficients of the finite impulse response (FIR) filter in a memory.
14. The method of claim 13 , wherein the memory is external to the compensator.
15. The method claim 9 , wherein applying the plurality of test signals further comprises:
generating the test signals with a self-calibration module located on the signal processing board.
16. The method claim 9 , wherein solving for coefficients of a vector h(n) further comprises: determining the coefficients of the vector h(n) with a self-calibration module located on the signal processing board.
17. A signal processing device within a distributed antenna system, the signal processing device comprising:
a signal path within a signal processing board, the signal path having an uncompensated distortion function of G(ω); and
a compensator coupled to the signal path, the compensator having a finite impulse response (FIR) filter with an impulse response function represented by a vector {right arrow over (h)} and having filter coefficients h(n) of vector {right arrow over (h)} that are based on the relationship {right arrow over (Y)}{right arrow over (h)}={right arrow over (d)}, wherein {right arrow over (d)} is a vector representing an input to the signal path subject to a delay and {right arrow over (Y)} is a convolution matrix for an estimated response of the signal path to a comb signal, the estimated response based on interpolated measured output responses of the signal path to a plurality of frequency sweep signal test inputs.
18. The signal processing device of claim 17 , further comprising a memory, wherein the filter coefficients h(n) for the vector {right arrow over (h)} are stored in the memory.
19. The signal processing device of claim 17 , further comprising a self-calibration module for calculating filter coefficients h(n) for the vector {right arrow over (h)}based on frequency sweep signals generated by the self-calibration module.
20. The signal processing device of claim 17 , wherein the signal path of the signal processing board comprises at least one of a digital-to-analog converter (DAC) a frequency up-converter, an analog-to-digital converter (ADC) or a frequency down-converter.