Reset circuit and system having reset circuit
View Patent ↗In a power-on detection circuit, a first connection node at which a first divided voltage is generated is connected to a second power supply line during activation of a power-down detection signal. Inactivation timing of the power-down detection signal is set earlier than an activation timing of a power-on detection signal. Therefore, the first transistor whose gate is connected to the first connection node is certainly turned off in the first half of a power-on period, which prevents the power-on detection signal from being activated during the power-on period. Further, a leak current flowing through the first transistor is reduced. In the second half of the power-on period, the power-on detection signal is certainly generated using the first divided voltage generated by the first dividing circuit. Thus, operating a reset circuit without malfunction and normally outputting a reset signal is possible disregarding behavior of a power supply voltage at power-on.
1. A reset circuit, comprising:
a power detection circuit which activates a power-on signal indicating a power-on state when a power supply voltage exceeds a first voltage and is initialized during activation of an initializing signal; and
a starter circuit which includes a resistor element, a cut-off switch, and a capacitor disposed in series between a power supply line and a ground line and outputs said initializing signal from a first connection node connecting the resistor element and said cut-off switch, wherein
said cut-off switch is turned off during the activation of said power-on signal.
2. The reset circuit according to claim 1 , wherein
said power detection circuit includes:
a power-on detection circuit which activates a power-on detection signal when the power supply voltage exceeds said first voltage;
a power-down detection circuit which activates a power-down detection signal when the power supply voltage becomes lower than a second voltage lower than said first voltage; and
a power detection control circuit which activates a reset signal in response to the activation of the power-on detection signal and inactivates said reset signal in response to the activation of the power-down detection signal, wherein
said power-on signal is either said power-on detection signal or said reset signal.
3. The reset circuit according to claim 2 , wherein
said starter circuit further includes a second clamping switch disposed between said first connection node and said ground line and turned on during the activation of said power-down detection signal.
4. The reset circuit according to claim 1 , wherein
said starter circuit further includes a first clamping switch disposed between a second connection node connecting said cut-off switch and said capacitor and said ground line and turned on during the activation of said power-on signal.
5. The reset circuit according to claim 4 , wherein
said power detection circuit includes:
a power-on detection circuit which activates a power-on detection signal when the power supply voltage exceeds said first voltage;
a power-down detection circuit which activates a power-down detection signal when the power supply voltage becomes lower than a second voltage lower than said first voltage; and
a power detection control circuit which activates a reset signal in response to the activation of the power-on detection signal and inactivates said reset signal in response to the activation of the power-down detection signal,
said power-on signal is either said power-on detection signal or said reset signal, and
said first clamping switch is further turned on during the activation of said power-down detection signal.
6. The reset circuit according to claim 1 , wherein
said capacitor is a ferroelectric capacitor.
7. A system including a semiconductor memory comprising:
a reset circuit which outputs a power-on signal to initialize an internal circuit of said semiconductor memory at power-on, wherein
the semiconductor memory includes ferroelectric memory cells,
wherein said reset circuit includes:
a power detection circuit which activates a power-on signal indicating a power-on state when a power supply voltage exceeds a first voltage and is initialized during activation of an initializing signal; and
a starter circuit which includes a resistor element, a cut-off switch, and a capacitor disposed in series between a power supply line and a ground line and outputs said initializing signal from a first connection node connecting the resistor element and said cut-off switch, wherein
said cut-off switch is turned off during the activation of said power-on signal.