IP Library Granted Patent US 8,143,725
Granted Patent B2
US 8,143,725 · App. 12/650,733 · Granted Mar 27, 2012

Semiconductor device

Assignee: Panasonic Corporation
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Quick Facts
Patent No.
US 8,143,725
App. No.
12/650,733
Granted
Mar 27, 2012
Kind
B2
Abstract

A semiconductor device includes a first interconnect 31 ; a second interconnect 32 which is formed in a different interconnect layer from that of the first interconnect 31 , and which has a wider line width than that of the first interconnect 31 ; and first and second plugs 51 and 52 which are formed in a region where the first and second interconnects 31 and 32 extend in the same direction so as to overlap one above the other, and which electrically connect the first and second interconnects 31 and 32 . The first plug 51 has a larger base area than that of the second plug 52 , and is formed on an end side of the first interconnect 31 with respect to the second plug 52.

Claims (44)

1. A semiconductor device, comprising:

a first interconnect;

a second interconnect which is formed in a different interconnect layer from that of the first interconnect, and which has a wider line width than that of the first interconnect; and

first and second plugs which are formed in a region where the first and second interconnects extend in the same direction so as to overlap one above the other, and which electrically connect the first and second interconnects,

wherein the first plug has a larger base area than that of the second plug, and is formed on an end side of the first interconnect with respect to the second plug, and

the first interconnect has greater resistivity than that of the second interconnect.

2. The semiconductor device of claim 1 , wherein

a base shape of the first plug is square or round, and

a base shape of the second plug is rectangular or ellipsoidal.

3. The semiconductor device of claim 1 , wherein the first plug has a length extending in a direction intersecting with the line width of the first interconnect, which is longer than that of the second plug.

4. The semiconductor device of claim 3 , wherein the first and second plugs have widths extending in a direction parallel to the line width of the first interconnect, which are equal to the line width of the first interconnect.

5. The semiconductor device of claim 1 , wherein a region where the first and second plugs are formed includes an end of the first interconnect.

6. The semiconductor device of claim 1 , further comprising:

a third plug which electrically connects the first and second interconnects, which is formed between the first and second plugs, and which has a base area smaller than that of the first plug, and larger than that of the second plug.

7. A semiconductor device, comprising:

a first interconnect;

a second interconnect which is formed in a different interconnect layer from that of the first interconnect, and which has a wider line width than that of the first interconnect; and

first and second plugs which are formed in a region where the first and second interconnects extend in the same direction so as to overlap one above the other, and which electrically connect the first and second interconnects,

wherein the first plug has a larger base area than that of the second plug, and is formed on an end side of the first interconnect with respect to the second plug, and

a sum of a resistance value between the first and second plugs in the first interconnect, and a resistance value of the first plug is equal to a sum of a resistance value between the first and second plugs in the second interconnect, and a resistance value of the second plug.

8. The semiconductor device of claim 7 , wherein

a base shape of the first plug is square or round, and

a base shape of the second plug is rectangular or ellipsoidal.

9. The semiconductor device of claim 7 , wherein the first plug has a length extending in a direction intersecting with the line width of the first interconnect, which is longer than that of the second plug.

10. The semiconductor device of claim 9 , wherein the first and second plugs have widths extending in a direction parallel to the line width of the first interconnect, which are equal to the line width of the first interconnect.

11. The semiconductor device of claim 7 , wherein a region where the first and second plugs are formed includes an end of the first interconnect.

12. The semiconductor device of claim 7 , further comprising:

a third plug which electrically connects the first and second interconnects, which is formed between the first and second plugs, and which has a base area smaller than that of the first plug, and larger than that of the second plug.

13. A semiconductor device, comprising:

a first interconnect;

a second interconnect which is formed in a different interconnect layer from that of the first interconnect, and which has a wider line width than that of the first interconnect; and

first and second plugs which are formed in a region where the first and second interconnects extend in the same direction so as to overlap one above the other, and which electrically connect the first and second interconnects,

wherein the first plug has a larger base area than that of the second plug, and is formed on an end side of the first interconnect with respect to the second plug,

the second interconnect is formed in an upper interconnect layer with respect to the first interconnect,

the first and second interconnects are copper interconnects having conductive barrier films, and

the first and second plugs are integrally formed with the second interconnect.

14. The semiconductor device of claim 13 , wherein

a base shape of the first plug is square or round, and

a base shape of the second plug is rectangular or ellipsoidal.

15. The semiconductor device of claim 13 , wherein the first plug has a length extending in a direction intersecting with the line width of the first interconnect, which is longer than that of the second plug.

16. The semiconductor device of claim 15 , wherein the first and second plugs have widths extending in a direction parallel to the line width of the first interconnect, which are equal to the line width of the first interconnect.

17. The semiconductor device of claim 13 , wherein a region where the first and second plugs are formed includes an end of the first interconnect.

18. The semiconductor device of claim 13 , further comprising:

a third plug which electrically connects the first and second interconnects, which is formed between the first and second plugs, and which has a base area smaller than that of the first plug, and larger than that of the second plug.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2015
From: PANASONIC CORPORATION
To: PANNOVA SEMIC, LLC
Reel/Frame 036065/0273 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2010
From: MOTOJIMA, DAI
To: PANASONIC CORPORATION
Reel/Frame 024021/0543 →
Priority Claims (1)
JP 2008-149554 · Jun 6, 2008 · national
Continuity (2)
Continuation PCTJP2009000712 · Feb 19, 2009
Related Publication 20100133690A1 · Jun 3, 2010