IP Library Granted Patent US 7,879,655
Granted Patent B2
US 7,879,655 · App. 12/685,403 · Granted Feb 1, 2011

Semiconductor device and a manufacturing method of the same

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Quick Facts
Patent No.
US 7,879,655
App. No.
12/685,403
Granted
Feb 1, 2011
Kind
B2
Abstract

A semiconductor device is disclosed wherein first wiring lines in a first row extend respectively from first connecting portions toward one side of a semiconductor chip, while second wiring lines extend respectively from second connecting portions toward the side opposite to the one side of the semiconductor chip. The reduction in size of the semiconductor device can be attained.

Claims (13)

1. A method of manufacturing a semiconductor device, comprising the steps of:

(a) providing a wiring substrate including an upper surface having a first side, a chip mounting portion formed on the upper surface, a plurality of first connecting portions arranged along the first side and arranged between the first side and the chip mounting portion in a plan view, a plurality of second connecting portions arranged along the first side and arranged between the first side and the plurality of first connecting portions in the plan view, a plurality of third connecting portions arranged along the first side and arranged between the first side and the plurality of second connecting portions in the plan view, and a lower surface opposed to the upper surface;

(b) mounting a semiconductor chip on the chip mounting portion, the semiconductor chip including a front surface having a second side, a plurality of bonding pads arranged along the second side, and a rear surface opposed to the front surface, the plurality of bonding pads including a plurality of first bonding pads, a second bonding pad and a third bonding pad, the plurality of first bonding pads having an outside bonding pad and an inside bonding pad, the second bonding pad being arranged between the outside bonding pad and the inside bonding pad, and the third bonding pad being arranged between the second bonding pad and the inside bonding pad;

(c) electrically coupling the plurality of first bonding pads and the plurality of first connecting portions with a plurality of first bonding wires;

(d) after the step (c), electrically coupling the second bonding pad and one of the plurality of second connecting portions with a second bonding wire such that a part of the second bonding wire is located above the plurality of first bonding wires; and

(e) after the step (d), electrically coupling the third bonding pad and one of the plurality of third connecting portions with a third bonding wire such that a part of the third bonding wire is located above the second bonding wire;

wherein a shape, in the plan view, of each of the plurality of bonding pads is a rectangular shape including a first part and a second part located farther than the first part from the second side in the plan view;

wherein in the step (c), each first bonding wire is connected with the first part of a corresponding one of the plurality of first bonding pads;

wherein in the step (e), the third bonding wire is connected with the second part of the third bonding pad; and

wherein, in the plan view, the plurality of first bonding wires, the second bonding wire and the third bonding wire extend from the plurality of bonding pads at acute angles with respect to a phantom line which is perpendicular to the second side and which intersects a center of the second side.

2. The method of manufacturing a semiconductor device according to claim 1 , wherein the steps (c), (d) and (e) are performed using a capillary.

3. The method of manufacturing a semiconductor device according to claim 2 , wherein after the step (e), the semiconductor chip, the plurality of first bonding wires, the second bonding wire and the third bonding wire are sealed with resin.

4. The method of manufacturing a semiconductor device according to claim 3 , wherein after sealing the semiconductor chip, the plurality of first bonding wires, the second bonding wire and the third bonding wire with resin, a plurality of external connecting terminals are formed on the lower surface of the wiring substrate.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Aug 13, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024864/0635 →
MERGER Recorded Aug 13, 2010
From: RENESAS TECHNOLOGY CORP.
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024879/0190 →