Semiconductor device and production method thereof
View Patent ↗A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.
1. A method of manufacturing a semiconductor device, comprising:
forming a gate insulating film over a silicon substrate;
forming a gate electrode over the gate insulating film;
implanting a first impurity having first conductivity into the silicon substrate using the gate electrode as a mask;
forming a first side wall insulating film on a side wall of the gate electrode, a portion of the first side wall insulating film extending over the silicon substrate;
forming a second side wall insulating film on the first side wall insulating film;
implanting a second impurity having the first conductivity into the silicon substrate using the gate electrode, the first side wall insulating film, and the second side wall insulating film as masks;
forming a trench in the silicon substrate by etching the silicon substrate using the gate electrode, the first side wall insulating film, and the second side wall insulating film as masks;
removing a portion of the first side wall insulating film to form a concave portion between the silicon substrate and the second sidewall insulating film;
forming a semiconductor mixed crystal layer in the trench and in the concave portion; and
performing a heat treatment to diffuse an impurity in the semiconductor mixed crystal layer formed in the concave portion into the silicon substrate.
2. The method as claimed in claim 1 , further comprising, between said forming of the gate electrode and said forming of the first side wall insulating film:
forming a third side wall insulating film on the side wall of the gate electrode, said third side wall insulating film and the first side wall insulating film being formed from different insulating materials each having etching selectivity.
3. The method as claimed in claim 2 , wherein
in said removing of the portion of the first side wall insulating film, a portion of the third side wall insulating film is exposed.
4. The method as claimed in claim 1 , wherein
the first side wall insulating film and the second side wall insulating film are formed from different insulating materials each having etching selectivity, and
in said removing of the portion of the first side wall insulating film, an etching solution is used to enable etching speed in the first side wall insulating film to be greater than etching speed in the second side wall insulating film.
5. A method of manufacturing a semiconductor device including a first MOS transistor of a first conductivity formed in a first region of a semiconductor substrate and a second MOS transistor of a second conductivity opposite to the first conductivity and formed in a second region of the semiconductor substrate, said method comprising:
forming a gate insulating film over a silicon substrate in the first region and the second region;
forming a gate electrode over the gate insulating film in the first region and the second region;
forming pocket implantation regions of the first conductivity and first diffusion regions of the second conductivity in the silicon substrate in the second region;
forming a first side wall insulating film on a side wall of the gate electrode in the first region and the second region, a portion of the first side wall insulating film extending over the silicon substrate;
forming a second side wall insulating film on the first side wall insulating film in the first region and the second region;
forming second diffusion regions of the first conductivity in the silicon substrate in the first region using the gate electrode, the first side wall insulating film, and the second side wall insulating film as masks, said second diffusion regions forming a source region and a drain region;
forming, by etching the silicon substrate, a trench in the first region in the silicon substrate using the gate electrode, the first side wall insulating film, and the second side wall insulating film as masks;
removing a portion of the first side wall insulating film in the first region to form a concave portion between the silicon substrate and the second side wall insulating film;
forming a semiconductor mixed crystal layer of the first conductivity in the trench and in the concave portion;
forming second diffusion regions of the second conductivity in the silicon substrate in the second region using the gate electrode, the first side wall insulating film, and the second side wall insulating film as masks;
and
performing a heat treatment to diffuse an impurity in the semiconductor mixed crystal layer formed in the concave portion into the silicon substrate.
6. The method as claimed in claim 5 , wherein
a thickness of the first side wall insulating film is in a range from 5 nm to 20 nm.
7. The method as claimed in claim 5 , wherein
the first side wall insulating film and the second side wall insulating film are formed from different insulating materials each having etching selectivity, and
in said removing of the portion of the first side wall insulating film, an etching solution is used to enable etching speed in the first side wall insulating film to be greater than etching speed in the second side wall insulating film.
8. A method of manufacturing a semiconductor device including a first MOS transistor of a first conductivity formed in a first region of a semiconductor substrate and a second MOS transistor of a second conductivity opposite to the first conductivity and formed in a second region of the semiconductor substrate, said method comprising:
forming a gate insulating film over a silicon substrate in the first region and the second region;
forming a gate electrode over the gate insulating film in the first region and the second region;
forming pocket implantation regions of the second conductivity and first diffusion regions of the first conductivity in the silicon substrate in the first region using the gate electrode as a mask;
forming pocket implantation regions of the first conductivity and first diffusion regions of the second conductivity in the silicon substrate in the second region using the gate electrode as a mask;
forming a first side wall insulating film on a side wall of the gate electrode in the first region and the second region, a portion of the first side wall insulating film extending over the silicon substrate;
forming a second side wall insulating film on the first side wall insulating film in the first region and the second region;
forming second diffusion regions of the first conductivity in the silicon substrate in the first region using the gate electrode, the first side wall insulating film, and the second side wall insulating film as masks, said second diffusion regions forming a source region and a drain region;
forming, by etching the silicon substrate, a trench in the first region in the silicon substrate using the gate electrode, the first side wall insulating film, and the second side wall insulating film as mask;
removing a portion of the first side wall insulating film in the first region to form a concave portion between the silicon substrate and the second side wall insulating film;
forming a semiconductor mixed crystal layer of the first conductivity in the trench;
forming second diffusion regions of the second conductivity in the silicon substrate in the second region using the gate electrode, the first side wall insulating film, and the second side wall insulating film as masks; and
forming, between said forming of the gate electrode and said forming of the first side wall insulating film, a third side wall insulating film on the side wall of the gate electrode, said third side wall insulating film and the first side wall insulating film being formed from different insulating materials each having etching selectivity.
9. The method as claimed in claim 8 , wherein
a thickness of the first side wall insulating film is in a range from 5 nm to 20 nm.