IP Library Granted Patent US 7,956,682
Granted Patent B2
US 7,956,682 · App. 12/702,349 · Granted Jun 7, 2011

Amplifier

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Quick Facts
Patent No.
US 7,956,682
App. No.
12/702,349
Granted
Jun 7, 2011
Kind
B2
Abstract

An amplifier including a first transistor including a gate coupled to an input terminal and a grounded source; a load resistor provided between a drain of the first transistor and a power supply; an output terminal coupled to a node between the drain of the first transistor and the load resistor; a feedback path coupled to the input terminal and the output terminal and including a resistor and a capacitor; a bias voltage generator applying a gate bias voltage to the gate of the first transistor in response to an enable signal; a supply resistor provided between an output node for the gate bias voltage of the bias voltage generator and the gate of the first transistor; and an enable switch lowering a resistance value between the output node for the gate bias voltage and a node in the feedback path.

Claims (58)

1. An amplifier comprising:

a first transistor including a gate coupled to an input terminal and a grounded source;

a load resistor provided between a drain of the first transistor and a power supply;

an output terminal coupled to a node between the drain of the first transistor and the load resistor;

a feedback path coupled to the input terminal and the output terminal and including a resistor and a capacitor;

a bias voltage generator applying a gate bias voltage to the gate of the first transistor in response to a first enable signal;

a supply resistor provided between an output node for the gate bias voltage of the bias voltage generator and the gate of the first transistor; and

an enable switch lowering a resistance value between the output node for the gate bias voltage and a node in the feedback path.

2. The amplifier according to claim 1 , comprising:

a second transistor cascode-coupled between the drain of the first transistor and the load resistor and including a gate to which a given bias voltage is supplied.

3. The amplifier according to claim 1 ,

wherein the enable switch is provided between the output node for the gate bias voltage and the input terminal, becomes temporarily conductive in response to a setup signal, and becomes non-conductive in an operating state.

4. The amplifier according to claim 1 ,

wherein the enable switch is provided between the output node for the gate bias voltage and a node in the feedback path, the enable switch becoming temporarily conductive in response to a setup signal and becoming non-conductive in an operating state.

5. The amplifier according to claim 1 ,

wherein the enable switch is provided between the output node for the gate bias voltage and a node in the supply resistor, becomes temporarily conductive in response to a setup signal, and becomes non-conductive in an operating state.

6. The amplifier according to claim 1 ,

wherein the input terminal receives a high frequency signal through a band pass filter, and

wherein an input impedance of the input terminal matches an output impedance of the band pass filter.

7. The amplifier according to claim 3 , comprising:

a setup signal generator generating the setup signal, the setup signal causing the enable switch to be conductive before the enable signal starts to be supplied and causing the enable switch to be non-conductive after a given time after the enable signal starts to be supplied.

8. An amplifier comprising:

a first transistor a gate of which is coupled to an input terminal and a source of which is grounded;

a second transistor cascode-coupled on the side of a drain of the first transistor and including a gate to which a given bias voltage is supplied;

a load resistor provided between a drain of the second transistor and a power supply;

an output terminal coupled to a node between the drain of the second transistor and the load resistor;

a feedback path coupled to the input terminal and the output terminal and including a resistor and a capacitor;

a bias voltage generator applying a gate bias voltage to the gate of the first transistor in response to an enable signal;

a supply resistor provided between an output node for the gate bias voltage of the bias voltage generator and the gate of the first transistor; and

an enable switch provided between the output node for the gate bias voltage and a node in the feedback path or a node between the input terminal and the gate of the first transistor, the enable switch becoming temporarily conductive in response to a setup signal and becoming non-conductive in an operating state.

9. The amplifier according to claim 8 ,

wherein the input terminal receives a high frequency signal through a band pass filter, and

wherein an input impedance of the input terminal matches an output impedance of the band pass filter.

10. The amplifier according to claim 8 , further comprising:

a setup signal generator generating the setup signal, the setup signal causing the enable switch to be conductive before the enable signal starts to be supplied and causing the enable switch to be non-conductive after a given time after the enable signal starts to be supplied.

11. A communication apparatus comprising:

a transmission and reception terminal;

an amplifier on a reception side to which a signal received at the transmission and reception terminal is supplied through a first band pass filter; and

an amplifier on a transmission side, outputting an output signal to the transmission and reception terminal through a second band pass filter;

wherein the amplifier on the reception side includes:

an input terminal to which the received signal is input;

a first transistor including a gate coupled to the input terminal and a grounded source;

a load resistor provided between a drain of the first transistor and a power supply;

an output terminal coupled to a node between the drain of the first transistor and the load resistor;

a feedback path coupled to the input terminal and the output terminal and including a resistor and a capacitor;

a bias voltage generator applying a gate bias voltage to the gate of the first transistor in response to an enable signal;

a supply resistor provided between an output node for the gate bias voltage of the bias voltage generator and the gate of the first transistor; and

an enable switch lowering a resistance value between the output node for the gate bias voltage and a node in the feedback path.

12. The communication apparatus according to claim 11 , wherein the amplifier on the reception side further includes:

a second transistor cascode-coupled between the drain of the first transistor and the load resistor and including a gate to which a given bias voltage is supplied.

13. The communication apparatus according to claim 11 , wherein

wherein the enable switch is provided between the output node for the gate bias voltage and the input terminal, becomes temporarily conductive in response to a setup signal, and becomes non-conductive in an operating state.

14. The communication apparatus according to claim 11 ,

wherein the enable switch is provided between the output node for the gate bias voltage and a node in the feedback path, the enable switch becoming temporarily conductive in response to a setup signal and becoming non-conductive in an operating state.

15. The communication apparatus according to claim 11 ,

wherein the enable switch is provided between the output node for the gate bias voltage and a node in the supply resistor, becomes temporarily conductive in response to a setup signal, and becomes non-conductive in an operating state.

16. The communication apparatus according to claim 11 , further comprising:

a setup signal generator generating a setup signal, the setup signal causing the enable switch to be conductive before the enable signal starts to be supplied and causing the enable switch to be non-conductive after a given time after the enable signal starts to be supplied.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035508/0637 →
CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NUMBER PREVIOUSLY RECORDED AT REEL: 025046 FRAME: 0478. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Feb 24, 2015
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 035090/0086 →
CHANGE OF NAME Recorded Sep 27, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 025046/0478 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2010
From: HASEGAWA, NOBUMASA
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 023960/0896 →