Manufacturing method of semiconductor device
In a modern 0.15 μm power MOSFET, aluminum voids (voids formed in an aluminum-type electrode) are generated frequently in trench portions (source contact trenches) caused by the reduction of a cell pitch for refinement. It is considered to be attributable to the defects which are generated mainly due to a sudden increase of the aspect ratio from 0.84 in the previous generation to 2.8 in the current generation. Accordingly, concave portions of repetitive trenches having a high aspect ratio are filled with an aluminum-type metal by ionized sputtering throughout the processing, from the formation to the filling of an aluminum-type metal seed film.
1. A manufacturing method of a semiconductor device comprising the steps of:
(a) forming downward a concave portion from an upper surface of a first insulator film over a first main surface of a semiconductor wafer;
(b) forming a barrier metal film to an inner surface of the concave portion and the upper surface of the first insulator film; and
(c) after the step (b), forming an aluminum-type metal layer so as to fill the inside of the concave portion and cover the upper surface of the first insulator film in a sputter processing chamber by ionized sputtering;
wherein the step (c) is conducted in a state of directing upward the first main surface of the semiconductor wafer to a wafer stage having an electrostatic chuck disposed in the sputter processing chamber,
wherein the step (c) includes the sub-steps of:
(c1) forming a seed aluminum-type metal layer so as to cover the barrier metal film at the inner surface of the concave portion and at the upper surface of the first insulator film; and
(c2) continuing the ionized sputtering thereby forming the aluminum-type metal layer to fill the inside of the concave portion and cover the upper surface of the first insulator film, and being integrated with the seed aluminum-type metal layer, and
wherein the electrostatic chuck is in an off state in the sub-step (c1) and the electrostatic chuck is in an on state in the sub-step (c2),
wherein a bias is applied by a second high frequency power for the electrode on the side of the wafer stage in the sub-step (c1), and
wherein a bias is not applied for the electrode on the side of the wafer stage in the sub-step (c2).
2. The manufacturing method of a semiconductor device according to claim 1 , wherein the temperature of the wafer stage is 400° C. or higher and lower than 440° C.
3. The manufacturing method of a semiconductor device according to claim 1 , wherein the sputter processing chamber is a magnetron type.
4. The manufacturing method of a semiconductor device according to claim 1 , wherein a first high frequency power and a DC bias are applied on the side of the target in the step (c).
5. The manufacturing method of a semiconductor device according to claim 1 , wherein the semiconductor device has a power MOSFET or IGBT.
6. The manufacturing method of a semiconductor device according to claim 5 , wherein the aluminum-type metal layer is the source electrode of the power MOSFET or the emitter electrode of the IGBT.
7. The manufacturing method of a semiconductor device according to claim 1 , wherein the aspect ratio of the concave portion is 2 or more.
8. The manufacturing method of a semiconductor device according to claim 1 , wherein the concave portion reaches as far as the inside of a bulk portion of the semiconductor wafer.