Switching controller for power converters

1. A switching controller for a power converter, comprising:

a current-sense circuit, receiving a high-voltage signal across a first switch to generate a current-sense signal, wherein said current-sense signal is representative of a switching current flowing through said first switch;

a first comparator, receiving a current-limit threshold and said current-sense signal for generating a first signal when said current-sense signal exceeding said current-limit threshold, wherein said current-limit threshold is utilized to limit a maximum of said switching current flowing through said first switch;

a second comparator, receiving a feedback signal and said current-sense signal, wherein said second comparator generates a second signal when said current-sense signal exceeds said feedback signal, wherein said feedback signal is correlated to an output voltage of said power converter;

a PWM circuit, coupled to said first comparator and said second comparator for generating a switching signal in response to said first signal and said second signal; and

a delay circuit, receiving said switching signal to generate a delayed switching signal, wherein said switching signal generated by said PWM circuit drives a control terminal of said first switch.

2. The switching controller as claimed in claim 1 , said current-sense circuit comprising:

a second switch, coupled to said first switch for receiving said high-voltage signal, wherein a control terminal of said second switch is driven by said delayed switching signal generated by said delay circuit;

a third switch, coupled to said second switch, said first comparator and said second comparator; and

an inverter, receiving said delayed switching signal generated by said delay circuit for controlling a control terminal of said third switch.

3. The switching controller as claimed in claim 2 , wherein said first switch and said second switch are high-voltage transistors.

4. The switching controller as claimed in claim 2 , wherein said current-sense signal and said high-voltage signal ramp up with the same slope during enabling of said delayed switching signal generated by said delay circuit.

5. The switching controller as claimed in claim 2 , wherein said third switch will be turned on to pull down said current-sense signal to a level of a ground reference during disabling of said delayed switching signal generated by said delay circuit.

6. The switching controller as claimed in claim 2 , wherein a delay time provided by said delay circuit avoids said high-voltage signal at the instance which said first switch is being turned off being conducted into said first comparator and said second comparator via said second switch.

7. A switching controller for a power converter, comprising:

a current-sense circuit, receiving a high-voltage signal across a first switch to generate a current-sense signal, wherein said current-sense signal is representative of a switching current flowing through said first switch;

a PWM circuit, generating a switching signal in response to said current-sense signal, wherein said switching signal drives said first switch; and

a delay circuit, receiving said switching signal to generate a delayed switching signal for controlling said current-sense circuit.

8. The switching controller as claimed in claim 7 , further comprising:

a first comparator, receiving a current-limit threshold and said current-sense signal for generating a first signal when said current-sense signal exceeding said current-limit threshold, wherein said current-limit threshold is utilized to limit a maximum of said switching current flowing through said first switch; and

a second comparator, receiving a feedback signal and said current-sense signal, wherein said second comparator generates a second signal when said current-sense signal exceeds said feedback signal, wherein said feedback signal is correlated to an output voltage of said power converter;

wherein, said PWM circuit generates said switching signal in response to said first signal and said second signal.

9. The switching controller as claimed in claim 7 , wherein said current-sense signal will be pulled down to a level of a ground reference during disabling of said delayed switching signal generated by said delay circuit.

10. The switching controller as claimed in claim 7 , said current-sense circuit comprising:

a second switch, coupled to said first switch for receiving said high-voltage signal, wherein said second switch is driven by said delayed switching signal generated by said delay circuit;

a third switch, coupled to said second switch; and

an inverter, receiving said delayed switching signal generated by said delay circuit for controlling said third switch.

11. The switching controller as claimed in claim 10 , wherein said third switch will be turned on to pull down said current-sense signal to a level of a ground reference during disabling of said delayed switching signal generated by said delay circuit.

12. The switching controller as claimed in claim 10 , wherein said second switch is a high-voltage transistor.

13. The switching controller as claimed in claim 7 , wherein said delay circuit provides a delay time, said delay time is inserted between the rising edges of said switching signal generated by said PWM circuit and said delayed switching signal generated by said delay circuit.

14. The switching controller as claimed in claim 7 , wherein said current-sense signal and said high-voltage signal ramp up with the same slope during enabling of said delayed switching signal generated by said delay circuit.

15. The switching controller as claimed in claim 7 , wherein said first switch is a high-voltage transistor.