IP Library Granted Patent US 8,736,732
Granted Patent B2
US 8,736,732 · App. 12/722,121 · Granted May 27, 2014

Analog to digital converter for solid-state image pickup device

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Quick Facts
Patent No.
US 8,736,732
App. No.
12/722,121
Granted
May 27, 2014
Kind
B2
Abstract

There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

Claims (25)

1. A solid-state image pickup device comprising:

an image unit, in which a plurality of pixels each including a photoelectric conversion element for converting an optical signal into an electrical signal are arranged in a matrix, for sequentially scanning pixels in each row and outputting pixel signals of a selected row through a plurality of vertical readout lines arranged in respective columns;

a plurality of holding units configured to hold pixel signals outputted through the vertical readout lines;

a plurality of conversion units, provided corresponding to the respective holding unit, each configured to convert a pixel signal held by corresponding holding unit from an analog signal to a digital value;

a first generation unit configured to generate first part bits of the digital value in accordance with the pixel signal held by the holding unit; and

a second generation unit configured to generate second part bits of the digital value in accordance with the pixel signal held by the holding unit and the first part bits generated by the first generation unit, wherein

each of the conversion units includes:

a comparison unit configured to determine a latch timing of the first part bits and the second part bits in accordance with the pixel signal;

an addition unit configured to add first part bits generated by the first generation unit and the second part bits generated by the second generation unit and outputting the digital value;

a plurality of capacitive elements which are capacitively coupled to a node at which the pixel signal is held by the holding unit;

a control unit configured to change a potential of the node in a stepwise manner by sequentially switching voltages of counter electrodes of the plurality of the capacitive elements; and

a determination unit configured to determine the latch timing of the first part bits of the digital value in accordance with a comparison result by the comparison unit,

the comparison unit compares the potential of the node with a predetermined potential and

the second generation unit includes:

a capacitive element which is capacitively coupled to the node at which the pixel signal is held by the holding unit;

a control unit configured to change a voltage of a counter electrode of the capacitive element in a slope manner; and

a counter value holding unit configured to determine the latch timing of the second part bits of the digital value in accordance with the comparison result by the comparison unit.

2. The solid-state image pickup device according to claim 1 ,

wherein the holding unit holds an exposed pixel signal, and

wherein the comparison unit compares a potential of a non-exposed pixel signal with a potential of the exposed pixel signal.

3. The solid-state image pickup device according to claim 1 , wherein the second generation unit is a Gray code counter.

4. The solid-state image pickup device according to claim 3 , the conversion unit further comprising a code conversion circuit configured to convert the Gray code counter value held by the counter value holding unit into a binary code.

5. The solid-state image pickup device according to claim 1 , wherein the comparison unit is a comparator, and two inputs are both in a floating state when compared.

6. The solid-state image pickup device according to claim 1 , wherein one conversion unit is provided in each column of the pixels arranged in a matrix.

7. The solid-state image pickup device according to claim 1 , wherein the conversion unit converts a pixel signal of one row from an analog signal to a digital value, and a corresponding holding unit holds a pixel signal of a next row concurrently.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Jun 24, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024591/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2010
From: UTSUNOMIYA, HIROTO; DOSAKA, KATSUMI; KATO, HIROSHI; MORISHITA, FUKASHI; SASAKI, FUMIYASU
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 024067/0949 →