Semiconductor device with output circuit arrangement
The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
1. A semiconductor device comprising:
a semiconductor chip;
a plurality of internal circuits;
a corresponding plurality of output circuits disposed in a row in the semiconductor chip, each said output circuit including a first MISFET and a second MISFET coupled to each other;
a plurality of bonding pads for outputting output signals in response to outputs of said plurality of internal circuits disposed in the semiconductor chip, each said bonding pad being overlapped with only one of said first MISFET and said second MISFET in each of said output circuits in cross sectional view;
a plurality of wirings, each said wiring being coupled to said first and second MISFETs in each of said output circuits;
a plurality of conductor plugs, each said conductor plugs being disposed between one of said bonding pads and one of said wirings, each said conductor plug being coupled to a corresponding one of said bonding pads and to a corresponding one of said wirings;
a grounding wiring different than said wirings disposed in a lower layer than said plurality of bonding pads and coupled to said first MISFET in each of said output circuits; and
a power supply wiring different than said wirings disposed in a lower layer than said plurality of bonding pads and coupled to the second MISFET in each of said output circuits,
wherein a gate electrode of each first MISFET and a gate electrode of each second MISFET each receive a signal from a corresponding internal circuit to output the corresponding output signal,
wherein each of said wirings and each of said conductor plugs are located between the first MISFET and the second MISFET in each of said output circuits in cross sectional view, and
wherein each of said wirings and each of said conductor plugs are located between the grounding wiring and the power supply wiring in cross sectional view.
2. A semiconductor device according to claim 1 ,
further comprising a plurality of protection circuits for protecting from a surge inputted from said bonding pads;
wherein each of the protection circuits includes a first protection diode and a second protection diode,
wherein the first and second protection diodes in each of the output circuits are each coupled to each of said bonding pads, and
wherein each of said conductor plugs is located between the first and second protection diodes in each of the output circuits in cross-sectional view.
3. A semiconductor device according to claim 1 ,
further comprising a plurality of protection circuits for protecting from a surge inputted from said bonding pads;
wherein each of the protection circuits includes a first resistance element and a second resistance element,
wherein the first and second resistance elements in each of said output circuits are each coupled to each of said bonding pads, and
wherein each of said conductor plugs located between the first and second resistance elements in each of said output circuits in cross-sectional view.
4. A semiconductor device according to claim 1 ,
wherein the first MISFET is an nMISFET and the second MISFET is a pMISFET.
5. A semiconductor device according to claim 4 ,
wherein each of the first and second MISFETS has a source and a drain, and
wherein the drain of the first MISFET and the drain of the second MISFET in each of the output circuits are coupled to each said wiring.
6. A semiconductor device according to claim 5 ,
wherein the grounding wiring is coupled to the source of the first MISFET in each of said output circuits, and
wherein the power supply wiring is coupled to the source of the second MISFET in each of said output circuits.
7. A semiconductor device according to claim 5 ,
wherein each of said bonding pads is coupled to the drain of the first MISFET and to the drain of the second MISFET in each of said output circuits.
8. A semiconductor device according to claim 1 ,
wherein a protective film is disposed over said bonding pads, and
wherein each of said bonding pads is partially exposed from the protective film.
9. A semiconductor device according to claim 8 ,
wherein the protective film is overlapped with said conductive plugs in cross-sectional view.
10. A semiconductor device according to claim 1 ,
wherein each of said bonding pads is comprised of aluminum, and
wherein the grounding wire, the power supply wiring, and each of said wirings are comprised of copper.
11. A semiconductor device according to claim 1 ,
wherein one of the power supply wiring and the grounding wiring is disposed directly below said plurality of bonding pads in cross-sectional view.