Pulse modulation A/D-converter with feedback

1. An A/D converter comprising

an input,

an output,

a D/A converting feedback and

a pulse width modulating forward path;

the D/A converting feedback comprising at least one feed-back path;

the feed-back path establishing a D/A conversion based on at least two D/A conversions subject to uncorrelated errors, wherein the uncorrelated errors are derived from substantially Gaussian jitter in a clock signal.

2. The A/D converter according to claim 1 , wherein said errors are jitter errors.

3. The A/D converter according to claim 1 , wherein said errors are derived from one or more error sources.

4. The A/D converter according to claim 1 , wherein the at least two D/A conversions are summed.

5. The A/D converter according to claim 1 , wherein the uncorrelated errors are established on a basis of one or more error sources.

6. The A/D converter according to claim 1 , wherein the D/A converting feedback comprises a multiple of serially-coupled latches.

7. The A/D converter according to claim 1 , wherein the uncorrelated errors are established on a basis of a number of parallel error sources.

8. The A/D converter according to claim 1 , wherein the D/A converting feedback comprises a multiple of latches coupled in parallel.

9. The A/D converter according to claim 1 , wherein the D/A converting feedback comprises a multi-level D/A-converter.

10. The A/D converter according to claim 9 , wherein the multi-level D/A converter comprises a binary weighed multi-level D/A-converter.

11. The A/D converter according to claim 1 , wherein the uncorrelated errors are established on a basis of one or more error sources by means of multiple outputs from a delay line.

12. The A/D converter according to claim 1 , wherein the D/A converting feedback comprises at least one monostable multivibrator or equivalent which converts a digital bitstream into an analog sum-of-bits.

13. The A/D converter according to claim 1 , wherein said D/A converting feedback path comprises oversampling means.

14. The A/D converter according to claim 1 , wherein said A/D-converter comprises a downsampler or decimator.

15. The A/D converter according to claim 1 , wherein said pulse width modulating forward path is self-oscillating.

16. The A/D converter according to claim 1 , wherein said A/D converter establishes a 3-level PWM signal.

17. The A/D converter according to claim 1 , wherein said A/D converter comprises a multi channel A/D converter.

18. A jitter consequence reducing D/A-converter comprising a jitter-robust intermediate signal established on a basis of a digital input signal, wherein the jitter-robust intermediate signal comprises a number of effective signal levels greater than a number of effective signal levels in the digital input signal.

19. The jitter consequence reducing D/A-converter according to claim 18 , comprising a filter and a multi-level D/A-converter.

20. The jitter consequence reducing D/A-converter according to claim 19 , wherein the multi-level D/A-converter comprises a binary-weighed multi-level D/A-converter.

21. The jitter consequence reducing D/A-converter according to claim 19 , wherein conversions for each level in the multi-level D/A-converter are subject to errors, and the errors for each level are uncorrelated and derived from one or more error sources.

22. The jitter consequence reducing D/A-converter according to claim 21 , wherein the errors are jitter errors.

23. The jitter consequence reducing D/A-converter according to claim 18 , wherein establishment of said jitter-robust intermediate signal comprises reducing, filtering, shaping or conditioning high frequency content of the digital input signal.

24. The jitter consequence reducing D/A-converter according to claim 18 , wherein the jitter consequence reducing D/A-converter comprises a filter; the filter comprising a high-frequency reducing, filtering, shaping or conditioning filter.

25. The jitter consequence reducing D/A-converter according to claim 18 , comprising a multi-channel D/A-converter.

26. The jitter consequence reducing D/A-converter according to claim 18 , comprising multiple jitter-robust, intermediate signals, filters and multi-level D/A-converters, together forming a multi-level jitter consequence reducing D/A-converter.

27. The jitter consequence reducing D/A-converter according to claim 18 , comprising at least one monostable multivibrator or equivalent adapted to convert a digital bitstream into an analog sum-of-bits-signal.

28. A pulse width modulated A/D-converter comprising feedback, wherein the feedback comprises a jitter consequence reducing D/A-converter comprising a jitter-robust intermediate signal established on a basis of a digital input signal, wherein the jitter-robust intermediate signal comprises a number of effective signal levels greater than a number of effective signal levels in the digital input signal.

29. The pulse width modulated A/D-converter according to claim 28 , wherein said pulse width modulated A/D-converter comprises an input, an output, a D/A converting feedback and a pulse width modulating forward path; the D/A converting feedback comprising at least one feed-back path; the feedback path establishing a D/A conversion based on at least two D/A conversions subject to uncorrelated errors.

30. A method for jitter consequence reduction in a feedback of a pulse width modulated A/D-converter, comprising establishing at least two D/A-conversions subject to uncorrelated errors, and combining said at least two D/A-conversions.

31. The method for jitter consequence reduction according to claim 30 , wherein said combining said at least two D/A-conversions is performed by summing.