Semiconductor device comprising a memory cell group having a gate width larger than a second memory cell group
View Patent ↗The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.
1. A semiconductor device comprising first and second nonvolatile memory elements formed over a semiconductor substrate,
wherein the first nonvolatile memory element has:
a first gate insulating film formed over the semiconductor substrate;
a first gate electrode formed over the first gate insulating film;
a first charge-storage film formed over the semiconductor substrate and over a side face of the first gate electrode;
a second gate electrode formed over the first charge storage film,
wherein the second nonvolatile memory element has:
a second gate insulating film formed over the semiconductor substrate;
a third gate electrode formed over the second gate insulating film;
a second charge-storage film formed over the semiconductor substrate and over a side face of the third gate electrode;
a fourth gate electrode formed over the second charge storage film,
wherein the second and fourth gate electrodes are each in a form of a side wall;
wherein a rewriting frequency of the second nonvolatile memory element greater than a rewriting frequency of the first nonvolatile memory element,
wherein, in a gate width direction, a width of the fourth gate electrode is larger than a width of the second gate electrode, and
wherein, in the gate length direction, a length of the second gate electrode is equal to a length of the fourth gate electrode.
2. The semiconductor device according to claim 1 ,
wherein a data writing operation of each nonvolatile memory element is performed by injecting hot electrons into the respective charge storage film thereof,
wherein a data erasing operation of each nonvolatile memory element is performed by injecting hot holes into the respective charge storage film thereof.
3. The semiconductor device according to claim 1 ,
wherein the first nonvolatile memory element is used for storing program data, and
wherein the second nonvolatile memory element is used for storing processed data.
4. The semiconductor device according to claim 1 ,
wherein each of the first, second, third and fourth gate electrodes includes a polysilicon film.
5. The semiconductor device according to claim 1 ,
wherein each of the of the first and second charge storage films includes a silicon nitride film.
6. The semiconductor device according to claim 1 ,
wherein each of the first and second charge storage films includes a silicon oxynitride film.
7. The semiconductor device according to claim 1 ,
wherein the first nonvolatile memory element has a first source region and first and drain region in the semiconductor substrate,
wherein the first and second gate electrodes are formed between the first source region and the first drain region in the gate length direction, and
wherein the third and fourth gate electrodes are formed between the second source region and the second drain region in the gate length direction.
8. The semiconductor device according to claim 1 ,
wherein, in the gate width direction, a width of the third gate electrode is larger than a width of the first gate electrode.