Semiconductor memory device having layout area reduced
View Patent ↗A metal supplying an N well voltage is provided in a first metal interconnection layer. The metal is electrically coupled to an active layer provided in an N well region by shared contacts so that the N well voltage is supplied to the N well region. A metal supplying a P well voltage is provided in a third metal interconnection layer. The metal supplying the N well voltage is formed using a metal in the first metal interconnection layer and thus does not require a piling region to the underlayer, and only a piling region to the underlayer of the metal for the P well voltage needs to be secured. Therefore, the length in the Y direction of a power feed cell can be reduced thereby reducing the layout area of the power feed cell.
1. A semiconductor memory device comprising:
a memory array having a plurality of memory cells arranged in a matrix of rows and columns;
a plurality of bit line pairs arranged corresponding to the respective memory cell columns;
a plurality of word lines arranged corresponding to the respective memory cell rows;
a plurality of first power supply lines supplying a first power supply voltage to the corresponding memory cells;
a plurality of second power supply lines supplying a second power supply voltage to the corresponding memory cells; and
a plurality of power feed cells provided corresponding to the respective memory cell columns, feeding a first P well region, a second P well region and a N well region extended in a column direction respectively, wherein
said memory cell including
a first and a second P-channel MOS load transistors arranged on said N well region, having source nodes supplied said first power supply voltage,
a first N-channel MOS diver transistor arranged on said first P well region, connected to said first P-channel MOS load transistor to configure a first inverter, having a source node supplied said second power supply voltage,
a second N-channel MOS diver transistor arranged on said second P well region, connected to said second P-channel MOS load transistor to configure a second inverter, having a source node supplied said second power supply voltage,
a first N-channel MOS access transistor arranged on said first P well region, connected to said first inverter, and
a second N-channel MOS access transistor arranged on said second P well region, connected to said second inverter, wherein
said power feed cell including
a third power supply line supplying a third power supply voltage to said N well region, and
a fourth power supply line supplying a fourth power supply voltage to said first and second P well regions, wherein
said third power supply line is structured on a first metal interconnection layer,
said first power supply line is structured on a second metal interconnection layer above said first connection layer, and
said fourth power supply line is structured on a third metal interconnection layer above said second connection layer.
2. The semiconductor memory device according to claim 1 ,
said N well region, said first P well region and said second N well region are arranged in the order of said first P well region, said N well region and said second N well region in said row direction.
3. A semiconductor memory device comprising:
a memory array having a plurality of memory cells arranged in a matrix of rows and columns;
a plurality of bit line pairs arranged corresponding to the respective memory cell columns;
a plurality of word lines arranged corresponding to the respective memory cell rows;
a plurality of first power supply lines supplying a first power supply voltage to the corresponding memory cells;
a plurality of second power supply lines supplying a second power supply voltage to the corresponding memory cells; and
a plurality of power feed cells provided corresponding to the respective memory cell columns, feeding a first P well region, a second P well region and a N well region extended in a column direction respectively, wherein
said memory cell including
a first and a second P-channel MOS load transistors formed on said N well region, having source nodes supplied said first power supply voltage,
a first N-channel MOS diver transistor formed on said first P well region, connected to said first P-channel MOS load transistor to configure a first inverter, having a source node supplied said second power supply voltage,
a second N-channel MOS diver transistor formed on said second P well region, connected to said second P-channel MOS load transistor to configure a second inverter, having a source node supplied said second power supply voltage,
a first N-channel MOS access transistor formed on said first P well region, connected to said first inverter, and
a second N-channel MOS access transistor formed on said second P well region, connected to said second inverter, wherein
said power feed cell including
a third power supply line electrically coupled to said N well region, supplying a third power supply voltage to said N well region, and
a fourth power supply line electrically coupled to said first and second P well regions, supplying a fourth power supply voltage to said first and second P well regions, wherein
said third power supply line is formed in a first metal interconnection layer,
said first power supply line is formed in a second metal interconnection layer above said first connection layer, and
said fourth power supply line is formed in a third metal interconnection layer above said second connection layer.