IP Library Granted Patent US 7,919,361
Granted Patent B2
US 7,919,361 · App. 12/800,639 · Granted Apr 5, 2011

Semiconductor package with position member

Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
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Quick Facts
Patent No.
US 7,919,361
App. No.
12/800,639
Granted
Apr 5, 2011
Kind
B2
Abstract

The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.

Claims (24)

1. A method for manufacturing a semiconductor package, the method comprising: providing a leadframe with a plurality of lead terminals and a die-attach pad; adhering a first position member to one side of the die-attach pad; disposing a die onto a surface of the die-attach pad opposite to the first position member, wherein the first position member is smaller than the die pad and configured to reduce vertical flexing of the die during a package assembly process; electrically connecting the die to the plurality of lead terminals; and encapsulating the leadframe, the die, the bonding wires, and at least a portion of the first position member with a molding compound to form the semiconductor package, wherein a surface of the first position member forms a portion of an exterior surface of the semiconductor package.

2. The method of claim 1 further comprising:

disposing a second position member onto a surface of the die opposite to the die-attach pad.

3. The method of claim 1 , wherein disposing the die and adhering the first position member includes using adhesives selected from the group consisting of: glue, paste, tape and deformable material.

4. The method of claim 1 , wherein electrically connecting the die to the lead terminals is accomplished by wire bonding.

5. The method of claim 1 , wherein the wire bonding is made of a material selected from the group consisting of: gold, copper, and aluminum.

6. The method of claim 1 , wherein the die-attach pad has a split die-attach pad design.

7. The method of claim 6 , wherein each part of the die-attach pad has a position member.

8. The method of claim 1 , wherein the leadframe is made of a material selected from the group consisting of: Cu, PPF, and Alloy 42.

9. The method of claim 1 , wherein the position member is made of a material selected from the group consisting of: Si, Cu, and Epoxy.

10. The method of claim 1 , wherein the first position member comprises thermal conductive materials, and wherein, when a thermally conductive adhesive material is used for position member attachment, exposure of the first position member at the surface of the semiconductor package enhances thermal performance of the semiconductor package.

11. The method of claim 1 , wherein the first position member is an integral part of the leadframe.

12. A method for manufacturing a semiconductor package, the method comprising: providing a leadframe with a plurality of lead terminals and a die-attach pad; disposing a die onto one side of the die-attach pad; disposing a first position member adjacent to a surface of the die-attach pad opposite the die; disposing a second position member adjacent a surface of the die opposite the die-attach pad, wherein the first and second position members are smaller than the die pad and configured to reduce vertical flexing of the die during a package assembly process: electrically connecting die to the plurality of lead terminals with a plurality of bonding wires; and encapsulating the leadframe, the die, the bonding wires, and at least a portion of each of the first and second position members with a molding compound to form the semiconductor package, wherein a surface of each of the first and second position members forms a portion of an exterior surface of the semiconductor package.

13. The method of claim 12 further comprising:

disposing the first and second position members in substantial alignment onto opposite sides of the die-attach pad and the die.

14. The method of claim 12 , wherein disposing the die and the first and second position members includes using adhesives selected from the group consisting of: glue, paste, tape and deformable material.

15. The method of claim 12 , wherein electrically connecting the die to the lead terminals is accomplished by wire bonding.

16. The method of claim 12 , wherein the wire bonding is made of a material selected from the group consisting of: gold, copper, and aluminum.

17. The method of claim 12 , wherein the die-attach pad has a split die-attach pad design.

18. The method of claim 17 , wherein each part of the die-attach pad has a position member.

19. The method of claim 12 , wherein the leadframe is made of a material selected from the group consisting of: Cu, PPF, and Alloy 42.

20. The method of claim 12 , wherein the first and second position members are made of a material selected from the group consisting of: Si, Cu, and Epoxy.

21. The method of claim 12 , wherein the first and second position members comprise thermally conductive materials, and wherein, when a thermally conductive adhesive material is used for position member attachment, exposure of the first and second position members at the surface of the semiconductor package enhances thermal performance of the semiconductor package.

22. The method of claim 12 , wherein the first and second position members are an integral part of the leadframe.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2024
From: STMICROELECTRONICS ASIA PACIFIC PTE LTD
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 068434/0215 →
Priority Claims (1)
SG 200506718-6 · Oct 14, 2005 · national
Continuity (2)
Division 11545814 · Oct 10, 2006
Related Publication 20100297813A1 · Nov 25, 2010