Semiconductor device having nonvolatile memory element and manufacturing method thereof
View Patent ↗To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of the antifuse elements are at a low level, and an exclusive OR circuit that outputs different logic information for a case that the logic states are different from each other and a case that they are same as each other.
1. A semiconductor device comprising:
first and second fuse elements each representing one of first and second states;
a first logic circuit coupled to the first and second fuse elements to produce a first logic level when the first fuse element is the same in state as the second fuse element and a second logic level when the first fuse element is different in state from the second fuse element; and
a second logic circuit coupled to the first and second fuse elements to produce one of the first and second logic levels when at least one of the first and second fuse elements is in the first state and the other of the first and second logic levels when each of the first and second fuse elements is in the second state.
2. The device as claimed in claim 1 , further comprising an input node supplied with a signal whose logic level is to be detected and a third logic circuit coupled to the input node and the second logic circuit to detect whether the logic level of the signal is equal to the logic level produced by the second logic circuit.
3. The device as claimed in claim 2 , further comprising a plurality of memory cells, the signal being a part of address information for selecting at least one of the memory cells.
4. A semiconductor device comprising:
first and second fuse elements each representing one of first and second states;
a first logic circuit coupled to the first and second fuse elements to produce a first logic level when the first fuse element is the same in state as the second fuse element and a second logic level when the first fuse element is different in state from the second fuse element; and
an internal circuit generating an data signal in a normal operation mode and an output circuit coupled to the internal circuit and the first logic circuit to output the data signal in the normal operation mode and a signal related to the logic level from the first logic circuit in test operation mode.
5. The device as claimed in claim 4 , wherein each of the first and second fuse elements may be blown by electrical power.
6. The device as claimed in claim 4 , wherein the first logic circuit comprises an Exclusive OR gate.
7. The device as claimed in claim 1 , wherein the first logic circuit comprises an Exclusive OR gate and the second logic circuit comprises an OR gate.
8. The device as claimed in claim 2 , wherein the first logic circuit comprises an Exclusive OR gate, the second logic circuit comprises an OR gate, and the third logic circuit comprises an Exclusive NOR gate.
9. The device as claimed in claim 4 , wherein each of the first and second fuse elements comprises a fuse that is electrically blown, and the fuse is configured such that a current flows therethrough by the fuse being electrically blown.
10. The device as claimed in claim 4 , wherein each of the first and second fuse elements comprises an anti-fuse.
11. A semiconductor device comprising:
first and second fuse elements each representing one of first and second states;
a first logic circuit operatively coupled to the first and second fuse elements, the first logic circuit being configured to produce a first logic level when the first fuse element is equal in state to the second fuse element and a second logic level when the first fuse element is different in state from the second fuse element; and
a second logic circuit operatively coupled to the first and second fuse elements, the second logic circuit being configured to produce one of the first and second logic levels when at least one of the first and second fuse elements is in the first state and the other of the first and second logic levels when each of the first and second fuse elements is in the second state.
12. The device as claimed in claim 11 , wherein the first logic circuit comprises an Exclusive OR gate, and the second logic circuit comprises an OR gate.
13. The device as claimed in claim 11 , further comprising an input node and a third logic, circuit, the input node being supplied with a signal, the third logic circuit being operatively coupled to the input node and the second logic circuit and configured to detect whether the logic level of the signal is equal to the logic level produced by the second logic circuit.
14. The device as claimed in claim 13 , wherein the first logic circuit comprises an Exclusive OR gate, the second logic circuit comprises an OR gate, and the third logic circuit comprises an Exclusive NOR gate.
15. The device as claimed in claim 4 , further comprising a second logic circuit coupled to the first and second fuse elements to produce one of the first and second logic levels when at least one of the first and second fuse elements is in the first state and the other of the first and second logic levels when both of the first and second fuse elements are in the second state.
16. The device as claimed in claim 15 , further comprising an input node supplied with a signal whose logic level is to be detected and a third logic circuit coupled to the input node and the second logic circuit to detect whether the logic level of the signal is equal to the logic level produced by the second logic circuit.
17. The device as claimed in claim 15 , wherein the first logic circuit comprises an Exclusive NOR gate and the second logic circuit comprises an OR gate.
18. The device as claimed in claim 16 , wherein the first logic circuit comprises an Exclusive Nor gate, the second logic circuit comprises an OR gate, and the third logic circuit comprises an Exclusive NOR gate.