Method of fabricating field effect transistors with different gate widths
View Patent ↗Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.
1. A method for manufacturing a semiconductor device comprising a first field effect transistor and a second field effect transistor, a gate width of said second field effect transistor being narrower than that of said first field effect transistor and a conduction type of said second field effect transistor coinciding with that of said first field effect transistor, said method comprising the steps of: forming a gate insulating film and a polysilicon film sequentially on a semiconductor substrate; introducing first impurities into a part of said polysilicon film; patterning said polysilicon film, thereby forming a first gate electrode into which said first impurities have been introduced for said first field effect transistor, and forming a second gate electrode into which said first impurities have not been introduced for said second field effect transistor; and introducing second impurities into said first and second gate electrodes.
2. The method for manufacturing a semiconductor device according to claim 1 , wherein a thickness of said gate insulating film is between 0.8 nm and 1.5 nm.
3. The method for manufacturing a semiconductor device according to claim 1 , wherein a gate width of said first field effect transistor is equal to or greater than 0.5 μm.
4. The method for manufacturing a semiconductor device according to claim 1 , wherein a gate width of said second field effect transistor is equal to or less than 0.5 μm.
5. The method for manufacturing a semiconductor device according to claim 1 , wherein said first and second impurities are phosphorus.
6. The method for manufacturing a semiconductor device according to claim 1 , wherein an impurity concentration in said second gate electrode is 60% to 70% of an impurity concentration in said first gate electrode.
7. The method for manufacturing a semiconductor device according to claim 1 , wherein said step of introducing said first impurities comprises the step of carrying out ion implantation into said part of said polysilicon film.
8. The method for manufacturing a semiconductor device according to claim 1 , wherein said step of introducing said second impurities comprises the step of carrying out ion implantation into said first and second gate electrodes.
9. The method for manufacturing a semiconductor device according to claim 1 , comprising the step of forming a memory cell including said second field effect transistor.