High resolution, high speed, miniaturized optical encoder
View Patent ↗Disclosed are various embodiments of a single track reflective optical encoder featuring current amplifiers disposed in the signal generating circuit thereof. Voltage amplifiers and their associated feedback resistors are eliminated in the various embodiments disclosed herein, resulting in decreased die size and improved encoder signal accuracy and performance, especially at high speeds The single track optical encoder configurations disclosed herein permit very high resolution reflective optical encoders in small packages to be provided. Methods of making and using such optical encoders are also disclosed.
1. A high resolution, high speed, single track optical encoder, comprising:
a light emitter configured to emit light therefrom;
a plurality of photodetectors or photodiodes having leading and trailing edges arranged along a single track and a common axis to form a single track light detector, the single track light detector having disposed along the common axis pairs of A and A\ data channel light detectors and B and B\ data channel light detectors, the A and B light detectors, and the A\ and B\ light detectors, respectively, being arranged to generate output signals that are 90 degrees out of phase with respect to one another, the A, A\ , B and B\ light detectors generating respective first, second, third and fourth output ramp signals;
signal generation circuitry comprising at least first, second, third and fourth current amplifiers configured to receive as inputs thereto, respectively, the first, second, third and fourth output ramp signals corresponding to the A, A\ , B and B\ light detectors, the first current amplifier, being configured to provide full A and fractional A output ramp signals, the second current amplifier being configured to provide full A\ and fractional A\ output ramp signals, the third current amplifier being configured to provide full B and fractional B output ramp signals, the fourth current amplifier being configured to provide full B\ and fractional B\ output ramp signals, the first, second, third and fourth current amplifiers having no amplification or filtering feedback loops operably connected to the inputs and outputs corresponding thereto, each of the current amplifiers generating full and fractional output ramp signals;
comparator circuitry configured to receive pairs of the A and fractional A output ramp signals, the A\ and fractional A\ output ramp signals, the B and fractional B output ramp signals, and the B\ and fractional B\ output ramp signals as inputs thereto, and to provide intermediate output signals therefrom; and
logic circuitry configured to receive the intermediate signals from the comparator circuitry and generate channel A and channel B output square wave or pulse signals on the basis of the intermediate signals.
2. The high resolution, high speed, single track optical encoder of claim 1 , wherein at least some of the fractional output ramp signals correspond to about one-third the amplitude of the full output ramp signals.
3. The high resolution, high speed, single track optical encoder of claim 1 , wherein at least some of the fractional output ramp signals correspond to about one-sixth the amplitude of the full output ramp signals.
4. The high resolution, high speed, single track optical encoder of claim 1 , wherein the signal generation circuitry, the comparator circuitry and the logic circuitry are implemented in a CMOS device.
5. The high resolution, high speed, single track optical encoder of claim 1 , wherein the signal generation circuitry, the comparator circuitry and the logic circuitry are implemented in a BiCMOS device.
6. The high resolution, high speed, single track optical encoder of claim 1 , wherein the signal generation circuitry, the comparator circuitry and the logic circuitry are implemented in a semiconductor integrated circuit device.
7. The high resolution, high speed, single track optical encoder of claim 1 , wherein the A\ and B\ light detectors are not located adjacent one another anywhere along the common axis and single track.
8. The high resolution, high speed, single track optical encoder of claim 1 , wherein widths of individual A, B, A\ and B\ light detectors range between about 1 microns and about 2 microns.
9. The high resolution, high speed, single track optical encoder of claim 1 , wherein a spacing between adjoining photodetectors or photodiodes arranged along the single track and the common axis is greater than or equal to a width of each of the photodetectors or photodiodes.
10. The high resolution, high speed, single track optical encoder of claim 1 , wherein the photodetectors or photodiodes are arranged along the single track and the common axis to form a sequential pattern or a repeating sequential pattern of photodetectors or photodiodes defined by (A, B, A\, B\).
11. The high resolution, high speed, single track optical encoder of claim 1 , wherein the photodetectors or photodiodes are arranged along the single track and the common axis to form a sequential pattern or a repeating sequential pattern of photodetectors or photodiodes defined by (A, A\, B, B\).
12. The high resolution, high speed, single track optical encoder of claim 1 , wherein the photodetectors or photodiodes are arranged along the single track and the common axis to form a sequential pattern or a repeating sequential pattern of photodetectors or photodiodes defined by (A, B\, A\, B).
13. The high resolution, high speed, single track optical encoder of claim 1 , wherein the photodetectors or photodiodes are arranged along the single track and the common axis to form a sequential pattern or a repeating sequential pattern of photodetectors or photodiodes defined by (A, B, A\, B\).
14. A method of making a high resolution, high speed, single track optical encoder, comprising:
providing a light emitter configured to emit light therefrom;
providing a plurality of photodetectors or photodiodes having leading and trailing edges arranged along a single track and a common axis to form a single track light detector, the single track light detector having disposed along the common axis a plurality of pairs of A and A\ data channel light detectors, and B and B\ data channel light detectors, the A and B light detectors, and the A\ and B\ light detectors, respectively, being arranged to generate output signals that are 90 degrees out of phase with respect to one another, the A, A\, B and B\ light detectors generating respective first, second, third and fourth output ramp signals;
providing signal generation circuitry comprising at least first, second, third and fourth current amplifiers configured to receive as inputs thereto, respectively, the first, second, third and fourth output ramp signals corresponding to the A, A\, B and B\ light detectors, the first current amplifier being configured to provide full A and fractional A output ramp signals, the second current amplifier being configured to provide full A\ and fractional A\ output ramp signals, the third current amplifier being configured to provide full B and fractional B output ramp signals, the fourth current amplifier being configured to provide full B\ and fractional B\ output ramp signals, the first, second, third and fourth current amplifiers having no amplification or filtering feedback loops operably connected to the inputs and outputs corresponding thereto, each of the current amplifiers generating full and fractional output ramp signals;
providing comparator circuitry configured to receive pairs of the A and fractional A output ramp signals, the A\ and fractional A\ output ramp signals, the B and fractional B output ramp signals, and the B\ and fractional B\ output ramp signals as inputs thereto, and to provide intermediate output signals therefrom; and
providing logic circuitry configured to receive the intermediate signals from the comparator circuitry and generate channel A and channel B output square wave or pulse signals on the basis of the intermediate signals.
15. The method of claim 14 , wherein at least some of the fractional output ramp signals correspond to about one-third the amplitude of the full output ramp signals.
16. The method of claim 14 , wherein at least some of the fractional output ramp signals correspond to about one-sixth the amplitude of the full output ramp signals.
17. The method of claim 14 , wherein the signal generation circuitry, the comparator circuitry and the logic circuitry are implemented in a CMOS device.
18. The method of claim 14 , wherein the signal generation circuitry, the comparator circuitry and the logic circuitry are implemented in a BiCMOS device.
19. The method of claim 14 , wherein the signal generation circuitry, the comparator circuitry and the logic circuitry are implemented in a semiconductor integrated circuit device.
20. The method of claim 14 , wherein a spacing between adjoining photodetectors or photodiodes arranged along the single track and the common axis is greater than or equal to a width of each of the photodetectors or photodiodes.
21. A method of encoding light signals generated by an optical encoder having a single track and a common axis, comprising:
emitting light from a light emitter towards a code scale;
reflecting at least a portion of the light emitted by the light emitter from the code scale, the code scale comprising alternating optically substantially reflective and substantially non-reflective data strips, the code scale being configured to travel along the common axis;
detecting at least a portion of the light reflected from the code scale with a plurality of photodetectors or photodiodes having leading and trailing edges arranged along the single track and the common axis to form a single track light detector, the single track light detector having disposed along the common axis a plurality of pairs of A and A\ data channel light detectors, and B and B\ data channel light detectors, the A and B light detectors, and the A\ and B\ light detectors, respectively, generating output signals that are 90 degrees out of phase with respect to one another, the A, A\ , B and B\ light detectors generating respective first, second, third and fourth output ramp signals;
generating full A and fractional A output ramp signals as outputs from a first current amplifier having the first output signal provided as an input thereto;
generating full A\ and fractional A\ output ramp signals as outputs from a second current amplifier having the second output signal provided as an input thereto;
generating full B and fractional B output ramp signals as outputs from a third current amplifier having the third output signal provided as an input thereto, and generating full B\ and fractional B\ output ramp signals as outputs from a fourth current amplifier having the fourth output signal provided as an input thereto;
wherein the first, second, third and fourth current amplifiers have no amplification or filtering feedback loops operably connected to the inputs and outputs corresponding thereto, each of the current amplifiers generating full and fractional output ramp signals.
22. The method of claim 21 , further comprising employing comparator circuitry to receive pairs of the A and fractional A output ramp signals, the A\ and fractional A\ output ramp signals, the B and fractional B output ramp signals, and the B\ and fractional B\ output ramp signals as inputs thereto, and to provide intermediate output signals therefrom.
23. The method of claim 21 , further comprising employing logic circuitry to receive the intermediate signals from the comparator circuitry and generate channel A and channel B output square wave or pulse signals on the basis of the intermediate signals.
24. The method of claim 21 , wherein at least some of the fractional output ramp signals correspond to about one-third the amplitude of the full output ramp signals.
25. The method of claim 21 , wherein at least some of the fractional output ramp signals correspond to about one-sixth the amplitude of the full output ramp signals.
26. The method of claim 21 , wherein the signal generation circuitry, the comparator circuitry and the logic circuitry are implemented in a CMOS device.
27. The method of claim 21 , wherein the signal generation circuitry, the comparator circuitry and the logic circuitry are implemented in a BiCMOS device.
28. The method of claim 21 , wherein the signal generation circuitry, the comparator circuitry and the logic circuitry are implemented in a semiconductor integrated circuit device.