Power-on reset circuit, module including same, and electronic device including same
View Patent ↗A power-on reset circuit includes a charge-up circuit to charge a first capacitor after power is on, a first NOR circuit connected to an output terminal of the charge-up circuit and receive a power-on reset signal output from an output terminal of the power-on reset circuit, a first inverter connected to the first NOR circuit, a second capacitor connected between an input terminal of the first NOR circuit and an output terminal of the first inverter, a counter configured to count a clock, a clock selector configured to select whether to output or inhibit a clock signal based on an output signal from the counter, and a second inverter connected to the output terminal of the counter to output the power-on reset signal.
1. A power-on reset circuit comprising:
a charge-up circuit to charge a first capacitor after power on;
a first NOR circuit to receive an output signal output from the charge-up circuit and a power-on reset signal output from an output terminal of the power-on reset circuit;
a first inverter connected to the first NOR circuit;
a second capacitor connected between an input terminal of the first NOR circuit and an output terminal of the first inverter;
a counter configured to count a clock;
a clock selector configured to select whether a clock signal is output or inhibited based on an output signal from the counter for output to the counter; and
a second inverter connected to the output terminal of the counter to output the power-on reset signal.
2. The power on reset circuit of claim 1 ,
wherein the charge-up circuit includes the first capacitor and a P-type MOS transistor to charge the first capacitor,
and a source of the P-type MOS transistor is connected to a first power supply, a gate of the P-type MOS transistor is connected to an output terminal of the first NOR circuit, one end of the first capacitor is connected to a drain of the P-type MOS transistor, another end of the first capacitor is connected to a second power supply, and an output signal is output from a junction node between the P-type MOS transistor and the first capacitor.
3. The power-on reset circuit of claim 1 ,
wherein the counter comprises at least one flip-flop circuit and receives an output signal of the clock selector, and the flip-flop circuit is controlled by the output signal of the clock selector to determine whether the counter is reset.
4. The power-on reset circuit of claim 1 ,
wherein the clock selector comprises a second NOR circuit which receives the clock signal and an output signal of the counter and output an output signal to the counter.
5. A module that employs the power-on reset circuit of claim 1 .
6. An electronic device that employs the power-on reset circuit of claim 1 .