Parallel video processing architecture
View Patent ↗The video data is parallel processed allowing for extremely fast video processing or a greatly reduced clock requirement for the video processing circuit. In operation, each video channel reads from main memory. This allows each video channel to track the laser directly. The Parallel video processor receives non-columnar pixel data, such as rows. The videoprocessor may support printers of any width without significantly increasing the size of the system.
1. A printer comprising:
a laser driver;
a print control engine; and
a video controller bidirectionally connected to each of the print control engine and the laser driver via a system bus, the video controller having a video block, wherein the video block includes
a direct memory access controller configured to receive a set of input pixels,
a parallel video processor wherein the parallel video processor comprises a series of 3N 2 bits per pixel input registers, wherein N is an integer, N≧1,
a first data bus and a first control bus electrically connecting the direct memory access controller to the parallel video processor,
a video signal generator connected to the parallel video processor,
a second data bus and a second control bus connecting the parallel video processor to the video signal generator, and
a third data bus and a third control bus electrically connecting the direct memory access controller to the system bus.
2. The printer of claim 1 , wherein the parallel video processor includes:
a first multiplexor configured to receive an upper half of the set of input pixels, the first multiplexor having an output connected to a top third of the series of input registers;
a second multiplexor configured to receive (i) output from the top third of the series of 3N 2 bits per pixel input registers, (ii) the upper half of the set of input pixels, and (iii) a lower half of the set of input pixels, the second multiplexor having an output connected to a middle third of the series of 3N 2 bits per pixel input registers;
a third multiplexor configured to receive (i) the lower half of the set of input pixels and (ii) an output from the middle third of the series of input registers, the third multiplexor having an output connected to the lower third of the series of 3N 2 bits per pixel input registers;
a fourth multiplexor configured to receive the output of the series of input registers, the fourth multiplexor being connected to a register “0”, where register “0” is a single 2 bits per pixel register; and
N logic blocks, each logic block m being configured to receive the outputs of the m+1 th and m th register of the series of input registers and either (i) the (m−1) th register of the series of 3N 2 bits per pixel input registers or (ii) register 0, wherein m is an integer and 1≦m≦N.
3. The printer of claim 2 , wherein the parallel video processor further includes N registers, each register being a 4-bit register, wherein each register m receives the outputs of the m th logic block.
4. The printer of claim 2 , wherein the set of input pixels includes 16 input pixels.
5. The printer of claim 2 , wherein N=4.
6. A printer comprising:
a laser driver;
a print control engine; and
a video controller bidirectionally connected to each of the print control engine and the laser driver via a system bus, the video controller having a video block, wherein the video block includes
a DMA memory reader configured to receive a set of input pixels corresponding to non-columnar pixel data across the system bus,
a parallel video processor configured to (i) receive each one of the set of input pixels and (ii) generate corresponding output videocodes, and
a video signal generator configured to receive the output videocodes in parallel and to generate an image corresponding to the output videocodes;
wherein the parallel video processor comprises a series of 3N 2 bits per pixel input registers, wherein N is an integer, N≧1,
wherein a lower third of the series of 3N 2 bits per pixel input registers is configured to selectively receive (i) a lower half of the set of input pixels or (ii) an output from one or more of the series of 3N 2 bits per pixel input registers;
wherein a middle third of the series of 3N 2 bits per pixel input registers is configured to selectively receive (i) a lower half of the set of input pixels, (ii) an upper half of the set of input pixels, or (iii) an output from one or more of the series of 3N 2 bits per pixel input registers; and
wherein a top third of the series of 3N 2 bits per pixel input registers is configured to either (i) receive an upper half of the set of input pixels or (ii) have the content of the top third of the series of 3N 2 bits per pixel input registers cleared.
7. The printer of claim 6 , wherein the parallel video processor further comprises a register “0” configured to selectively receive an output from at least one of the series of 3N 2 bits per pixel input registers.
8. The printer of claim 6 , wherein the set of input pixels includes 16 input pixels.
9. The printer of claim 6 , wherein the non-columnar pixel data relates to pixels that are adjacent and in the same row.
10. The printer of claim 6 , wherein N=4.