Semiconductor device and its manufacturing method
View Patent ↗A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.
1. A semiconductor device comprising:
a semiconductor substrate having a principal surface;
an isolation trench formed on the principal surface of said semiconductor substrate, said isolation trench defining first and second active regions and having a portion with an aspect ratio of 1 or larger;
an isolation region including a field region and made of an insulator embedded in said isolation trench;
a gate insulating film formed on surfaces of said first and second active regions;
a first gate electrode formed on said gate insulating film, said first gate electrode traversing said first active region and containing phosphorus at a high concentration;
a second gate electrode formed on said gate insulating film, said second gate electrode traversing said second active region and containing p-type impurities;
a p-type resistor element formed on said field region and made of a same layer as a layer of said second gate electrode;
a salicide block layer formed on a partial surface of said resistor element;
side wall spacers formed on side walls of said first and second gate electrodes;
first source/drain regions formed in said first active region outside the side wall spacers and containing phosphorus at a high concentration;
second source/drain regions formed in said second active region outside the side wall spacers and containing p-type impurities; and
salicide layers formed on surfaces of said resistor element not covered by the salicide block layer, at least partial surfaces of said first and second source/drain regions, and at least partial surfaces of said first and second gate electrodes.
2. The semiconductor device according to claim 1 , wherein a width of said gate electrodes is 0.2 μm or narrower.
3. The semiconductor device according to claim 1 , wherein said first source/drain regions have a peak phosphorus concentration of 1×10 20 cm −3 or larger.
4. The semiconductor device according to claim 1 , further comprising a salicide block layer formed on a partial surface of said first or second source/drain regions wherein said salicide layer on said source/drain regions is formed on a surface of said source/drain regions not covered with said salicide block layer.
5. The semiconductor device according to claim 1 , wherein said isolation trench defines also third to sixth active regions in which SRAM circuits are formed.