Semiconductor device, method of manufacturing the same, and method of evaluating semiconductor device
View Patent ↗A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate.
1. A method of manufacturing a semiconductor device, comprising the steps of: forming a gate insulating film on a semiconductor substrate; forming a gate electrode on the gate insulating film; forming a sidewall on a side surface of the gate electrode; forming a hole in the semiconductor substrate beside the gate electrode using any one of an organic alkaline solution and a tetramethylammonium hydroxide (TMAH) solution as an etchant, after forming the sidewall; and forming a source/drain material layer in the hole; wherein in the step of forming the hole, a thickness of the gate electrode is reduced by the etchant, and the method further comprises, after the step of forming the hole, the steps of: forming a refractory metal layer on the source/drain material layer and the gate electrode; and causing a reaction between the refractory metal layer and the gate electrode by heating the refractory metal layer and siliciding the entire gate electrode.
2. The method according to claim 1 , further comprising, before the step of forming the hole, the step of introducing p-type impurities into the gate electrode.
3. The method according to claim 1 , further comprising, before the step of forming the hole, the steps of:
forming a first conductivity type impurity diffusion region in the silicon substrate; and
forming a second conductivity type impurity diffusion region in the silicon substrate more deeply than the first conductivity type impurity diffusion region,
wherein, in the step of forming the hole, the hole is formed more deeply than the first conductivity type impurity diffusion region.
4. The method according to claim 3 ,
wherein, in the step of forming the first conductivity type impurity diffusion region, impurities of a first conductivity type are introduced into the silicon substrate using the gate electrode as a mask to form a source/drain extension, and the source/drain extension is used as the first conductivity type impurity diffusion region, and
in the step of forming the second conductivity type impurity diffusion region, impurities of a second conductivity type are introduced into the silicon substrate using the gate electrode and the sidewall as a mask.
5. The method according to claim 4 ,
wherein the step of forming the sidewall includes the steps of: forming a first sidewall on a side surface of the gate electrode; and forming a second sidewall on a side surface of the first sidewall, and
the method further comprises, after the step of forming the first sidewall, the step of forming a source/drain region by introducing impurities of the first conductivity type into the silicon substrate using the first sidewall as a mask.
6. The method according to claim 3 , wherein a p-type impurity diffusion region is formed as the first conductivity type impurity diffusion region, and an n-type impurity diffusion region is formed as the second conductivity type impurity diffusion region.
7. The method according to claim 3 , wherein a p-type impurity diffusion region is formed as the first conductivity type impurity diffusion region, and a p-type impurity diffusion region having a higher impurity concentration than that in the first conductivity type impurity diffusion region is formed as the second conductivity type impurity diffusion region.
8. The method according to claim 7 , wherein any one of a source/drain extension and a source/drain region is formed as the first conductivity type impurity diffusion region.
9. The method according to claim 1 , wherein an SOI substrate is used as the semiconductor substrate.
10. The method according to claim 1 , wherein a silicon substrate is used as the semiconductor substrate.
11. The method according to claim 10 , wherein a substrate with (001) surface orientation is used as the silicon substrate.
12. The method according to claim 10 ,
wherein a substrate with (110) surface orientation is used as the silicon substrate, and
in the step of forming the gate electrode, the gate electrode is formed with a gate width direction being set to a [111] direction.
13. The method according to claim 10 ,
wherein a substrate with (110) surface orientation is used as the silicon substrate, and
in the step of forming the gate electrode, the gate electrode is formed with a gate width direction being set to a [100] direction.
14. The method according to claim 1 , wherein a length by which an upper end portion of the hole goes under the sidewall is controlled by adjusting a substrate temperature when the sidewall is formed.
15. The method according to claim 1 , wherein a mixed solution of an ammonium hydroxide solution and isopropyl alcohol (IPA) is used as the organic alkaline solution.
16. The method according to claim 1 , wherein a SiGe layer is epitaxially grown as the source/drain material layer.
17. The method according to claim 1 , wherein a metal layer is formed as the source/drain material layer.