IP Library Granted Patent US 8,368,132
Granted Patent B2
US 8,368,132 · App. 12/873,720 · Granted Feb 5, 2013

Ferroelectric memory and manufacturing method thereof

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Quick Facts
Patent No.
US 8,368,132
App. No.
12/873,720
Granted
Feb 5, 2013
Kind
B2
Abstract

Provided is a ferroelectric memory including a silicon substrate, a transistor formed on the silicon substrate, and a ferroelectric capacitor formed above the transistor. The ferroelectric capacitor includes a lower electrode, a ferroelectric film formed on the lower electrode, an upper electrode formed on the ferroelectric film, and a metal film formed on the upper electrode.

Claims (38)

1. A ferroelectric memory comprising:

a semiconductor substrate;

a transistor formed on the semiconductor substrate; and

a ferroelectric capacitor formed over the transistor, wherein the ferroelectric capacitor includes:

a lower electrode;

a ferroelectric film formed over the lower electrode;

an upper electrode formed over the ferroelectric film;

a metal film formed over the upper electrode;

an insulating film covering the ferroelectric capacitor;

a hole formed through the insulating film and the metal film; and

a conductive plug formed in the hole and being contact to the upper electrode.

2. The ferroelectric memory according to claim 1 , wherein the upper electrode has a laminated structure of a first oxide film and a second oxide film.

3. The ferroelectric memory according to claim 2 , wherein each of the first oxide film and the second oxide film is an iridium oxide film.

4. The ferroelectric memory according to claim 1 , wherein the metal film contains titanium.

5. The ferroelectric memory according to claim 1 , wherein the metal film is made of noble metal.

6. The ferroelectric memory according to claim 5 , further comprising:

an insulating film covering the ferroelectric capacitor and including a hole over the metal film; and

a conductive plug formed in the hole and electrically connected to the upper electrode, wherein

a concave portion is formed in the metal film below the hole.

7. The ferroelectric memory according to claim 1 , wherein the metal film has a film thickness in a range from 20 nm to 30 nm.

8. A method of manufacturing a ferroelectric memory, comprising:

forming a transistor on a semiconductor substrate;

forming a lower electrode film over the transistor;

forming a ferroelectric film over the lower electrode film;

forming a first upper electrode film over the ferroelectric film;

forming a second upper electrode film over the first upper electrode film; and

forming a metal film over the second upper electrode film;

forming an insulating film covering the ferroelectric capacitor;

forming a hole through the insulating film and the metal film; and

forming a conductive plug in the hole, the conductive plug being contact to the upper electrode.

9. The method of manufacturing a ferroelectric memory according to claim 8 , further comprising:

forming the hole through in the metal film by wet etching after forming the hole through the insulating film.

10. The method of manufacturing a ferroelectric memory according to claim 9 , wherein the wet etching uses an etchant with which the metal film is etched at a faster etching rate than the first upper electrode film and the second upper electrode film are etched.

11. The method of manufacturing a ferroelectric memory according to claim 10 , wherein

oxide iridium films are formed as the first upper electrode film and the second upper electrode film,

a film containing titanium is formed as the metal film, and

an ammonium hydrogen peroxide mixture is used as the etchant.

12. The method of manufacturing a ferroelectric memory according to claim 8 , wherein a noble metal film is formed as the metal film.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED
Reel/Frame 053195/0249 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2010
From: NAGAI, KOUICHI
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024942/0779 →