Manufacturing method of semiconductor device comprising active region divided by STI element isolation structure
The active region of an NMOS transistor and the active region of a PMOS transistor are divided by an STI element isolation structure. The STI element isolation structure is made up of a first element isolation structure formed so as to include the interval between both active regions, and a second element isolation structure formed in the region other than the first element isolation structure.
1. A manufacturing method of a semiconductor device in which first and second active regions are divided by an element isolation structure formed in an element isolation region on a semiconductor substrate, and first and second conductivity type elements are formed in said first and second active regions, respectively,
said element isolation region comprising a first element isolation region including regions adjacent to a pair of opposed ends of said second active region, and a second element isolation region other than said first element isolation region,
said method comprising:
forming a first trench in said second element isolation region on said semiconductor substrate, and filling up said first trench with a first insulating material that gives a tensile stress to each of said first and second active regions; and
forming a second trench in said first element isolation region on said semiconductor substrate, and filling up said second trench with a second insulating material that gives a compressive stress to said second active region,
wherein said first insulating material is a different material from said second insulating material,
wherein said second insulating material is provided only in said second trench,
wherein, in said first active region, at least three of four sides are surrounded by said second element isolation region, and
wherein, in said second active region, a pair of opposed sides is surrounded by said first element isolation region and the other pair of opposed sides is surrounded by said second element isolation region.
2. The method according to claim 1 , further comprising forming a gate electrode into a pattern on each of said first and second active regions with a gate insulating film being interposed, so that the gate electrode on said second active region extends parallel to said first element isolation region.
3. The method according to claim 1 , wherein upper and lower layer portions of said first element isolation region are filled with different insulating materials that give compressive stresses.
4. The method according to claim 1 , wherein said insulating material that gives a compressive stress is one selected from a group of highly dense plasma oxide, oxide of amorphous silicon, and oxide of polycrystalline silicon, and said insulating material that gives a tensile stress is silicon oxide deposited at a temperature not more than a glass transition temperature of the silicon oxide.
5. A manufacturing method of a semiconductor device in which first and second active regions are divided by an element isolation structure formed in an element isolation region on a semiconductor substrate, and first and second conductivity type elements are formed in said first and second active regions, respectively,
said element isolation region comprising a first element isolation region including regions adjacent to a pair of opposed ends of said second active region, and a second element isolation region other than said first element isolation region,
said method comprising:
forming a first trench in said second element isolation region on said semiconductor substrate, and filling up said first trench with a first insulating material that gives a tensile stress to each of said first and second active regions; and
forming a second trench in a portion of said insulating material having filled up said first trench to give a tensile stress, corresponding to said first element isolation region, and filling up said second trench with a second insulating material that gives a compressive stress to said second active region,
wherein said first insulating material is a different material from said second insulating material,
wherein said second insulating material is provided only in said second trench,
wherein, in said first active region, at least three of four sides are surrounded by said second element isolation region, and
wherein, in said second active region, a pair of opposed sides is surrounded by said first element isolation region and the other pair of opposed sides is surrounded by said second element isolation region.
6. The method according to claim 5 , further comprising forming a gate electrode into a pattern on each of said first and second active regions with a gate insulating film being interposed, so that the gate electrode on said second active region extends parallel to said first element isolation region.
7. The method according to claim 5 , wherein said insulating material that gives a compressive stress is one selected from a group of highly dense plasma oxide, oxide of amorphous silicon, and oxide of polycrystalline silicon, and said insulating material that gives a tensile stress is silicon oxide deposited at a temperature not more than its glass transition temperature.