Method for fabricating semiconductor device and semiconductor device

1. A method for fabricating a semiconductor device, the method comprising steps of:

forming a plurality of lower interconnections including a first lower interconnection and a second lower interconnection adjacent to the first lower interconnection, at intervals in a first insulating film;

removing a portion of the first insulating film located between the lower interconnections, thereby forming an interconnection-to-interconnection gap;

burying a low-dielectric-constant film in the interconnection-to-interconnection gap;

forming a second insulating film over the first insulating film in which the lower interconnections and the low-dielectric-constant film are buried; and

forming, in the second insulating film, a connection portion connected to the first lower interconnection, and an upper interconnection connected to the connection portion, wherein:

in the forming of the interconnection-to-interconnection gap, no first insulating film is removed in a space between the first lower interconnection and the second lower interconnection, in a cross sectional view, along a direction perpendicular to the first and second lower interconnections, including the first lower interconnection, the second lower interconnection and the connection portion.

2. The method of claim 1 , wherein

the surfaces of the lower interconnections are lower than the surface of the first insulating film.

3. The method of claim 1 , wherein

an interconnection-to-interconnection space X between the lower interconnections sandwiching the low-dielectric-constant film satisfies the following relationship:

S=X

where S is a minimum interconnection-to-interconnection space between the lower interconnections formed at a minimum resolution of lithography.

4. The method of claim 1 , wherein the low-dielectric-constant film is located, from the connection portion, at least at a distance y satisfying the following relationship:

y=S +( L/ 2)

where S is a minimum interconnection-to-interconnection space between the lower interconnections formed at a minimum resolution of lithography and L is a minimum interconnection width of the lower interconnections formed at the minimum resolution of lithography.

5. The method of claim 1 , wherein

the interconnection-to-interconnection gap is formed using a resist pattern as a mask, and

the resist pattern has an opening pattern for exposing a region which is located between the lower interconnections and in which the interconnection-to-interconnection gap is to be formed and a region expanded from that region toward the lower interconnections sandwiching the region by a distance z satisfying the following relationship:

z=L/ 2

where L is the minimum interconnection width of the lower interconnections formed at the minimum resolution of lithography.

6. The method of claim 1 , wherein

the method further comprises the step of selectively forming a cap layer on each of the surfaces of the lower interconnections, after the step of forming the lower interconnections and before the step of forming the interconnection-to-interconnection gap.

7. A method for fabricating a semiconductor device, the method comprising the steps of:

forming a plurality of lower interconnections at intervals in a first insulating film;

removing a portion of the first insulating film located between the lower interconnections, thereby forming an interconnection-to-interconnection gap;

burying a low-dielectric-constant film in the interconnection-to-interconnection gap;

forming a second insulating film over the first insulating film in which the lower interconnections and the low-dielectric-constant film are buried;

forming, in the second insulating film, a connection portion connected to one of the lower interconnections and an upper interconnection connected to the connection portion; and

selectively forming a cap layer on each of the surfaces of the lower interconnections, after the step of forming the lower interconnections and before the step of forming the interconnection-to-interconnection gap

wherein the connection portion is formed to be connected to one of the lower interconnections not adjacent to the low-dielectric-constant film.

8. A method for fabricating a semiconductor device, the method comprising steps of:

forming a first insulating film on a semiconductor substrate;

forming recesses on a surface of the first insulating film from an upper surface of the first insulating film, the recesses constituting interconnect trenches adjoining each other with a space therebetween;

forming a plurality of lower interconnections including a first lower interconnection and a second lower interconnection adjacent to each other, at intervals by forming a conductive film in the interconnect trenches;

removing a portion of the first insulating film located between the lower interconnections, thereby forming an interconnection-to-interconnection gap

burying a low-dielectric-constant film in the interconnection-to-interconnection gap;

forming a second insulating film over the first insulating film in which the lower interconnections and the low-dielectric-constant film are buried; and

forming, in the second insulating film, a connection portion connected to the first lower interconnection, and an upper interconnection connected to the connection portion,

wherein the low-dielectric-constant film is not formed in a space between the first lower interconnection and the second lower interconnection, in a cross sectional view, along a direction perpendicular to the first and second lower interconnections, including the first lower interconnection, the second lower interconnection and the connection portion.

9. The method of claim 8 , wherein

the method further comprises the step of selectively forming a cap layer on each of the surfaces of the lower interconnections, after the step of forming the lower interconnections and before the step of forming the interconnection-to-interconnection gap.

10. The method of claim 8 , wherein

the surfaces of the lower interconnections are lower than the surface of the first insulating film.

11. The method of claim 8 , wherein

an interconnection-to-interconnection space X between the lower interconnections sandwiching the low-dielectric-constant film satisfies the following relationship:

S=X

where S is a minimum interconnection-to-interconnection space between the lower interconnections formed at a minimum resolution of lithography.

12. The method of claim 8 , wherein the low-dielectric-constant film is located, from the connection portion, at least at a distance y satisfying the following relationship:

y=S +( L/ 2)

where S is a minimum interconnection-to-interconnection space between the lower interconnections formed at a minimum resolution of lithography and L is a minimum interconnection width of the lower interconnections formed at the minimum resolution of lithography.

13. The method of claim 8 , wherein

the interconnection-to-interconnection gap is formed using a resist pattern as a mask, and

the resist pattern has an opening pattern for exposing a region which is located between the lower interconnections and in which the interconnection-to-interconnection gap is to be formed and a region expanded from that region toward the lower interconnections sandwiching the region by a distance z satisfying the following relationship:

z=L/ 2

where L is the minimum interconnection width of the lower interconnections formed at the minimum resolution of lithography.