Method and system for decoding single antenna interference cancellation (SAIC) and redundancy processing adaptation using frame process
View Patent ↗Aspects of a method and system for decoding single antenna interference cancellation (SAIC) and redundancy processing adaptation using frame process are provided. A receiver may decode video, voice, and/or speech bit sequences based on a first decoding algorithm that may utilize data redundancy and that may impose physical constraints. The receiver may also decode a bit sequence based on a second decoding algorithm that utilizes SAIC. The first and second decoding algorithms may be adapted to perform in parallel and a decoded received bit sequence may be selected based on a redundancy verification parameter. The first and second decoding algorithms may also be adapted to be performed sequentially where the subsequent decoding operation may be conditioned to the initial decoding operation. Moreover, either the first or the second decoding algorithm may be selected for decoding the received bit sequence. The selection may be based on noise and/or interference measurements.
1. A method for signal processing, the method comprising:
performing, by one or more processors and/or circuits:
selecting a first decoding algorithm or a second decoding algorithm, the selection being based on one or both of a noise level associated with a received bit sequence and an interference level associated with the received bit sequence;
decoding the received bit sequence utilizing the selected decoding algorithm, wherein:
the first decoding algorithm utilizes redundancy and imposes at least one physical constraint during decoding; and
the second decoding algorithm utilizes single antenna interference cancellation (SAIC).
2. The method according to claim 1 , wherein the physical constraint is related to a type of data for the received bit sequence.
3. The method according to claim 1 , comprising detecting one or both of the noise level associated with the received bit sequence and the interference level associated with the received bit sequence based on a colored noise detection algorithm.
4. The method according to claim 1 , comprising detecting one or both of the noise level associated with the received bit sequence and the interference level associated with the received bit sequence based on a signal level associated with the received bit sequence and on a signal-to-noise ratio (SNR) associated with the received bit sequence.
5. The method according to claim 4 , comprising determining an average value of the signal level associated with the received bit sequence and an average value of the SNR associated with the received bit sequence over a determined burst length.
6. The method according to claim 5 , comprising selecting the decoding algorithm from the first decoding algorithm and the second decoding algorithm based on the determined average value of the signal level associated with the received bit sequence and on the determined average value of the SNR associated with the received bit sequence.
7. The method according to claim 1 , comprising performing a burst process (BP) operation for the first decoding algorithm when the first decoding algorithm is the selected decoding algorithm.
8. The method according to claim 7 , comprising performing a frame process (FP) operation for the first decoding algorithm.
9. The method according to claim 1 , comprising performing a burst process (BP) operation for the second decoding algorithm when the second decoding algorithm is the selected decoding algorithm.
10. The method according to claim 9 , comprising performing a frame process (FP) operation for the second decoding algorithm.
11. A system for signal processing, the system comprising:
at least one processor that is operable to select a first decoding algorithm or a second decoding algorithm, the selection being based on one or both of a noise level associated with a received bit sequence and an interference level associated with the received bit sequence; and
the at least one processor is operable to decode the received bit sequence utilizing the selected decoding algorithm, wherein:
the first decoding algorithm utilizes redundancy and imposes at least one physical constraint during decoding; and
the second decoding algorithm utilizes single antenna interference cancellation (SAIC).
12. The system according to claim 11 , wherein the physical constraint is related to a type of data for the received bit sequence.
13. The system according to claim 11 , wherein the at least one processor is operable to detect one or both of the noise level associated with the received bit sequence and the interference level associated with the received bit sequence based on a colored noise detection algorithm.
14. The system according to claim 11 , wherein the at least one processor is operable to detect one or both of the noise level associated with the received bit sequence and the interference level associated with the received bit sequence based on a signal level associated with the received bit sequence and on a signal-to-noise ratio (SNR) associated with the received bit sequence.
15. The system according to claim 14 , wherein the at least one processor is operable to determine an average value of the signal level associated with the received bit sequence and an average value of the SNR associated with the received bit sequence over a determined burst length.
16. The system according to claim 15 , wherein the at least one processor is operable to select the decoding algorithm from the first decoding algorithm and the second decoding algorithm based on the determined average value of the signal level associated with the received bit sequence and on the determined average value of the SNR associated with the received bit sequence.
17. The system according to claim 11 , wherein the at least one processor is operable to perform a burst process (BP) operation for the first decoding algorithm when the first decoding algorithm is the selected decoding algorithm.
18. The system according to claim 17 , wherein the at least one processor is operable to perform a frame process (FP) operation for the first decoding algorithm.
19. The system according to claim 11 , wherein the at least one processor is operable to perform a burst process (BP) operation for the second decoding algorithm when the second decoding algorithm is the selected decoding algorithm.
20. The system according to claim 19 , wherein the at least one processor is operable to perform a frame process (FP) operation for the second decoding algorithm.