Power saving semiconductor memory
View Patent ↗A semiconductor memory, such as an SRAM, is described that accommodates smaller read/write accesses in one mode of operation and larger read/write accesses in a second mode of operation, wherein power is conserved during the smaller accesses. Methods of using such a semiconductor memory are also described.
1. A method for writing data to an array of memory cells arranged as a plurality of rows and a plurality of columns, comprising:
selecting an individual row from the plurality of rows based on one or more first address signals;
selecting a series of columns from the plurality of columns based on one or more second address signals, wherein the series of columns corresponds to the largest amount of data that can be written to the array of memory cells at one time;
determining whether a control signal is active; and
responsive to determining that the control signal is active,
activating write circuits associated only with a subset of the columns in the series of columns, and
writing data only to memory cells located in both the selected row and in the columns associated with the activated write circuits, thereby writing an amount of data that is smaller than the largest amount of data that can be written to the array of memory cells at one time.
2. The method of claim 1 , wherein the array of memory cells comprises an array of static random access memory (SRAM) cells.
3. The method of claim 1 , wherein selecting a series of columns from the plurality of columns comprises:
selecting a number of columns corresponding to a word of data, wherein a word of data includes a greater number of bits than a byte of data.
4. The method of claim 3 , wherein activating write circuits associated only with a subset of the columns in the series of columns comprises:
activating write circuits associated with a number of columns corresponding to a byte of data.
5. The method of claim 1 , further comprising:
responsive to determining that the control signal is not active, activating write circuits associated with each of the columns in the series of columns, and
writing data only to memory cells located in both the selected row and in the columns associated with the activated write circuits.
6. A semiconductor memory, comprising:
an array of memory cells arranged as a plurality of rows and a plurality of columns;
a row decoder coupled to the array of memory cells and configured to select an individual row from the plurality of rows based on one or more first address signals;
a first column decoder coupled to the array of memory cells and configured to select a series of columns from the plurality of columns based on one or more second address signals, wherein the series of columns corresponds to the largest amount of data that can be written to the array of memory cells at one time;
a second column decoder coupled to the first column decoder and the array of memory cells, the second column decoder configured to determine whether a control signal is active and, responsive to determining that the control signal is active, to activate write circuits associated only with a subset of the columns in the series of columns and to write data only to memory cells located in both the selected row and in the columns associated with the activated write circuits, thereby writing an amount of data that is smaller than the largest amount of data that can be written to the array of memory cells at one time.
7. The semiconductor memory of claim 6 , wherein the array of memory cells comprises an array of static random access memory (SRAM) cells.
8. The semiconductor memory of claim 6 , wherein the first column decoder is configured to select a series of columns from the plurality of columns by selecting a number of columns corresponding to a word of data, wherein a word of data includes a greater number of bits than a byte of data.
9. The semiconductor memory of claim 8 , wherein the second column decoder is configured to activate write circuits associated only with a subset of the columns in the series of columns by activating write circuits associated with a number of columns corresponding to a byte of data.
10. The semiconductor memory of claim 6 , wherein the second column decoder is further configured, responsive to determining that the control signal is not active, to activate write circuits associated with each of the columns in the series of columns and to write data only to memory cells located in both the selected row and in the columns associated with the activated write circuits.