Analog to digital converter with dynamic power configuration
View Patent ↗In an embodiment, an analog to digital converter (ADC) has a dynamic power circuit. The ADC has a track-and-hold circuit with an output and a track mode. The ADC also has a comparator with an input. A preamplifier is coupled between the track-and-hold output and the comparator input. At least one of a preamplifier current and a comparator current are limited during the track mode to reduce ADC power consumption.
1. An analog to digital converter (ADC), comprising:
a track-and-hold circuit configured to provide a track-and-hold output based on a signal received at an input of the ADC and based on whether the track-and-hold circuit is operating in a track mode or a hold mode;
a comparator configured to provide a comparator output based on the track-and-hold output, the comparator comprising a first pair of cross-coupled transistors, a second pair of cross-coupled transistors, and a differential pair of transistors; and
a dynamic power circuit configured to selectively turn on and off the first pair of cross-coupled transistors, the second pair of cross-coupled transistors, and the differential pair of transistors based on whether the track-and-hold circuit is operating in a first or second phase of time associated with the track mode, or in a third or fourth phase of time associated with the hold mode,
wherein the first phase occurs before the second phase, and the third phase occurs before the fourth phase.
2. The ADC of claim 1 , wherein the dynamic power circuit is configured to control the differential pair of transistors to be on and the first and second pair of cross-coupled transistors to be off during the first phase.
3. The ADC of claim 2 , wherein the differential pair of transistors, during the first phase, is configured to amplify the track-and-hold output and provide the amplified track-and-hold output at the comparator output.
4. The ADC of claim 1 , wherein the dynamic power circuit is configured to control the differential pair of transistors and the first pair of cross-coupled transistors to be on and the second pair of cross-coupled transistors to be off during the second phase.
5. The ADC of claim 4 , wherein the differential pair of transistors and the first pair of cross-coupled transistors, during the second phase, are configured to amplify the track-and-hold output and provide the amplified track-and-hold output at the comparator output.
6. The ADC of claim 1 , wherein the dynamic power circuit is configured to control the first and second pair of cross-coupled transistors to be on and the differential pair of transistors to be off during the third phase.
7. The ADC of claim 6 , wherein the first and second pair of cross-coupled transistors, during the third phase, are configured to pull the comparator output to a logical high or low value based on the track-and-hold output.
8. The ADC of claim 1 , wherein the dynamic power circuit is configured to control the first and second pair of cross-coupled transistors and the differential pair of transistors to be off during the fourth phase.
9. A method for controlling an analog to digital converter (ADC), comprising:
providing a track-and-hold output based on a signal received at an input of the ADC and based on whether the ADC is operating in a track mode or a hold mode;
providing a comparator output, based on the track-and-hold output, using a comparator that comprises a first pair of cross-coupled transistors, a second pair of cross-coupled transistors, and a differential pair of transistors; and
selectively turning on and off the first pair of cross-coupled transistors, the second pair of cross-coupled transistors, and the differential pair of transistors based on whether the ADC is operating in a first or second phase of time associated with the track mode, or in a third or fourth phase of time associated with the hold mode,
wherein the first phase occurs before the second phase, and the third phase occurs before the fourth phase.
10. The method of claim 9 , wherein the step of selectively turning on and off the first pair of cross-couple transistors, the second pair of cross-coupled transistors, and the differential pair of transistors, further comprises:
controlling the differential pair of transistors to be on and the first and second pair of cross-coupled transistors to be off during the first phase.
11. The method of claim 10 , wherein the differential pair of transistors, during the first phase, is configured to amplify the track-and-hold output and provide the amplified track-and-hold output at the comparator output.
12. The method of claim 9 , wherein the step of selectively turning on and off the first pair of cross-couple transistors, the second pair of cross-coupled transistors, and the differential pair of transistors, further comprises:
controlling the differential pair of transistors and the first pair of cross-coupled transistors to be on and the second pair of cross-coupled transistors to be off during the second phase.
13. The method of claim 12 , wherein the differential pair of transistors and the first pair of cross-coupled transistors, during the second phase, are configured to amplify the track-and-hold output and provide the amplified track-and-hold output at the comparator output.
14. The method of claim 9 , wherein the step of selectively turning on and off the first pair of cross-couple transistors, the second pair of cross-coupled transistors, and the differential pair of transistors, further comprises:
controlling the first and second pair of cross-coupled transistors to be on and the differential pair of transistors to be off during the third phase.
15. The method of claim 14 , wherein the first and second pair of cross-coupled transistors, during the third phase, are configured to pull the comparator output to a logical high or low value based on the track-and-hold output.
16. The ADC of claim 9 , wherein the step of selectively turning on and off the first pair of cross-couple transistors, the second pair of cross-coupled transistors, and the differential pair of transistors, further comprises:
controlling the first and second pair of cross-coupled transistors and the differential pair of transistors to be off during the fourth phase.
17. An analog to digital converter (ADC), comprising:
a track-and-hold circuit configured to provide a track-and-hold output based on a signal received at an input of the ADC and based on whether the track-and-hold circuit is operating in a track mode or a hold mode;
a comparator configured to provide a comparator output based on the track-and-hold output, the comparator comprising a comparator core and a comparator amplifier; and
a dynamic power circuit configured to selectively turn on and off the comparator core and the comparator amplifier based on whether the track-and-hold circuit is operating in a first or second phase of time associated with the track mode, or in a third or fourth phase of time associated with the hold mode,
wherein the first phase occurs before the second phase, and the third phase occurs before the fourth phase.
18. The ADC of claim 17 , wherein the comparator core includes a first pair of cross-coupled transistors and a second pair of cross-coupled transistors.
19. The ADC of claim 18 , wherein the dynamic power circuit is configured to control the comparator amplifier to be on and the first and second pair of cross-coupled transistors to be off during the first phase.
20. The ADC of claim 18 , wherein the dynamic power circuit is configured to control the comparator amplifier and the first pair of cross-coupled transistors to be on and the second pair of cross-coupled transistors to be off during the second phase.
21. The ADC of claim 18 , wherein the dynamic power circuit is configured to control the first and second pair of cross-coupled transistors to be on and the comparator amplifier to be off during the third phase.
22. The ADC of claim 18 , wherein the dynamic power circuit is configured to control the first and second pair of cross-coupled transistors and the comparator amplifier to be off during the fourth phase.