Semiconductor device and production method thereof
A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.
1. A semiconductor device, comprising:
a silicon substrate;
a gate insulating film formed over the silicon substrate;
a gate electrode formed over the gate insulating film;
a first side wall insulating film formed on a side wall of the gate electrode and on the silicon substrate;
a second side wall insulating film formed on the first side wall insulating film;
a source extension region and a drain extension region having a first conductivity type formed in the silicon substrate;
a source region and a drain region having the first conductivity type formed in the silicon substrate in contact with the source extension region and the drain extension region respectively;
trenches formed in the source region and the drain region;
concave portions between a bottom surface of the second side wall insulating film and the silicon substrate; and
semiconductor mixed crystal layers formed in the trenches and the concave portions and in contact with a side surface of the second side wall insulating film.
2. The semiconductor device as claimed in claim 1 , wherein the silicon substrate has a (100) plane as a principal plane; and
a gate electrode direction of the gate electrode on the silicon substrate is approximately a <110> direction or approximately a <100> direction.
3. The semiconductor device as claimed in claim 1 , wherein side surfaces of the trenches formed in the silicon substrate include facets.
4. The semiconductor device as claimed in claim 3 , wherein the facets have wedge shape.
5. The semiconductor device as claimed in claim 4 , wherein the facets include upper facets and lower facets meeting at a front end of the wedge shape,
the lower facets are formed so that a distance between a lower surface of the trench formed in the source region and a lower surface of the trench formed in the drain region decreases toward an upper part of the lower facets, and
the upper facets are formed so that a distance between an upper surface of the trench formed in the source region and an upper surface of the trench formed in the drain region increases toward an upper part of the upper facets.
6. The semiconductor device as claimed in claim 3 , wherein the facets include flat planes.
7. The semiconductor device as claimed in claim 3 , wherein the facets include crystalline planes.
8. The semiconductor device as claimed in claim 1 , wherein the first side wall insulating film and the second side wall insulating film are formed from insulating materials having different etching characteristic.
9. The semiconductor device as claimed in claim 1 , further comprising:
an element separation region in the silicon substrate; and
a hydrofluoric acid resistant film covering the whole element separation region.
10. The semiconductor device as claimed in claim 1 , wherein the first conductivity type is p-type, and the semiconductor mixed crystal layer is a SiGe mixed crystal layer including a p-type impurity, and
a concentration of Ge in the SiGe mixed crystal layer is below 40 atom %.
11. The semiconductor device as claimed in claim 8 , wherein the SiGe mixed crystal layer includes a B impurity, and
a concentration of B in the SiGe mixed crystal layer is in a range from 1×10 19 cm −3 to 1×10 21 cm −3 .
12. The semiconductor device as claimed in claim 1 , wherein at least one of said facets is formed along a Si(111) plane.
13. The semiconductor device as claimed in claim 1 ,
wherein the first conductivity type is n-type, and the semiconductor mixed crystal layer is a SiC mixed crystal layer including a n-type impurity.
14. The semiconductor device as claimed in claim 1 ,
the semiconductor mixed crystal layers formed in the concave
portions are in contact with a portion of the source extension region and the drain extension region.
15. The semiconductor device as claimed in claim 1 , wherein the semiconductor mixed crystal layers has a first portion formed in the trenches and a second portion formed in the concave portions, and a bottom of the first portion is positioned lower than a bottom of the second portion.