IP Library Granted Patent US 9,257,751
Granted Patent B2
US 9,257,751 · App. 12/920,053 · Granted Feb 9, 2016

Integration of microstrip antenna with CMOS transceiver

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Quick Facts
Patent No.
US 9,257,751
App. No.
12/920,053
Granted
Feb 9, 2016
Kind
B2
Abstract

A monolithic antenna element comprises a microstrip patch antenna and a ground plane, with a substrate between the patch antenna and the ground plane. A feeding via extends from the ground plane layer through the substrate to the patch antenna, connecting to the antenna distal from lateral edges of the antenna. A coplanar waveguide (CPW) feed line is formed in the ground plane layer, and interrupts and is electrically distinct from the ground plane. The CPW extends from a lateral edge of the ground layer to the feeding via. The antenna can be flip chip bonded to a CMOS die, reducing cost of millimeter wave transceivers, e.g. 57-64 GHz. The antenna is fabricated using standard PCB technology and a single substrate for the antenna. Antenna arrays can be fabricated. Appropriately designed antenna feeds, flip chip interconnects and antenna shape provide suitably broad antenna bandwidth, with relatively high efficiency.

Claims (27)

1. A monolithic antenna element comprising:

a microstrip patch antenna formed on a first surface of a substrate;

a ground plane formed on or adjacent to a second surface of the substrate substantially opposite the first surface, such that, the substrate is between the patch antenna and the ground plane;

a feeding via extending from the second surface through the substrate to the first surface and being electrically connected to the microstrip patch antenna in a location distal from lateral edges of the microstrip patch antenna; and

a coplanar waveguide feed line formed on or adjacent to the second surface of the substrate and interrupting and being electrically distinct from the ground plane, and extending from proximal to a lateral edge of the second surface to the feeding via,

wherein the coplanar waveguide feed line is formed to connect with a feed line on a CMOS die such that the substrate is flip chip mountable entirely upon the CMOS die.

2. The monolithic antenna element of claim 1 wherein the patch antenna is substantially square shaped to provide circular polarization.

3. The monolithic antenna element of claim 1 wherein a location at which the feeding via is connected to the patch antenna is predetermined in a manner to effect input impedance matching.

4. The monolithic antenna element of claim 1 , wherein the patch antenna is substantially square shaped to provide circular polarization, and wherein impedance matching is effected by locating the feeding via substantially upon one diagonal of the patch antenna.

5. The monolithic antenna element of claim 1 , wherein the ground layer is formed on the second surface of the substrate, prior to flip chip mounting of the substrate upon a CMOS die.

6. The monolithic antenna element of claim 1 , wherein the ground layer is formed on a CMOS die and positioned adjacent to the second surface of the substrate by flip chip mounting of the substrate upon the CMOS die.

7. A monolithic transceiver comprising at least one antenna element in accordance with claim 1 flip chip mounted upon, a CMOS die.

8. The monolithic transceiver of claim 7 , wherein a size and position of metallic bumps upon the CMOS die provided to effect a flip chip interconnect with the antenna element are selected in order to optimize the antenna characteristics for an intended purpose.

9. The monolithic transceiver of claim 7 comprising a plurality of antenna elements in accordance with claim 1 flip chip mounted upon the CMOS die.

10. The monolithic transceiver of claim 9 wherein a single set of bumps is provided to feed all of the antenna elements.

11. The monolithic transceiver of claim 9 wherein a plurality of sets of bumps is provided, each set feeding a respective antenna element.

12. A method of fabricating a monolithic antenna element, the method comprising:

forming on a first surface of a substrate a microstrip patch antenna;

forming on or adjacent to a second surface of the substrate substantially opposite the first surface a ground plane, such that the substrate is between the patch antenna and the ground plane;

forming a feeding via extending from the second surface through the substrate to the first surface and being electrically connected to the microstrip patch antenna in a location distal from lateral edges of the microstrip patch antenna; and

forming on or adjacent to the second surface of the substrate a coplanar waveguide feed line interrupting and being electrically distinct from the ground plane, and extending from proximal to a lateral edge of the second surface to the feeding via,

wherein the coplanar waveguide feed line is formed to connect with a feed line on a CMOS die such that the substrate is flip chip mountable entirely upon the CMOS die.

13. The method of claim 1 wherein the patch antenna is substantially square shaped to provide circular polarization.

14. The method of claim 12 wherein a location at which the feeding via is connected to the patch antenna is predetermined in a manner to effect input impedance matching.

15. The method of claim 12 , wherein the patch antenna is substantially square shaped to provide circular polarization, and wherein impedance matching is effected by locating the feeding via substantially upon one diagonal of the patch antenna.

16. The method of claim 12 , wherein the ground layer is formed on the second surface of the substrate, prior to flip chip mounting of the substrate upon a CMOS die.

17. The method of claim 12 , wherein the ground layer is formed on a CMOS die and positioned adjacent to the second surface of the substrate by flip chip mounting of the substrate upon the CMOS die.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2017
From: NITERO, INC.; NITERO PTY. LTD.
To: ADVANCED MICRO DEVICES, INC.; AMD FAR EAST LTD.
Reel/Frame 041966/0913 →
CORRECTIVE ASSIGNMENT TO CORRECT THE DATE OF EXECUTION ON THE ASSIGNMENT PREVIOUSLY RECORDED ON REEL 030191 FRAME 0270. ASSIGNOR(S) HEREBY CONFIRMS THE IMPROPERLY ENTERED DATE OF 05/16/2001. IT SHOULD READ 05/16/2011. Recorded Jun 4, 2013
From: NATIONAL ICT AUSTRALIA LIMITED
To: NICTA IPR PTY LIMITED
Reel/Frame 030639/0447 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2013
From: NICTA IPR PTY LIMITED
To: NITERO PTY LIMITED
Reel/Frame 030200/0622 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2013
From: NATIONAL ICT AUSTRALIA LIMITED
To: NICTA IPR PTY LIMITED
Reel/Frame 030191/0270 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2011
From: FELIC, GORDANA; SKAFIDAS, STAN
To: NATIONAL ICT AUSTRALIA LIMITED
Reel/Frame 026128/0674 →