System and method for uncoded bit error rate equalization via interleaving
View Patent ↗A device, method, and computer readable medium for programming a codeword are presented. The method includes writing a first codeword portion to portions of nonvolatile memory rows, and writing a second codeword portion to portions of nonvolatile memory rows, wherein the first group of memory rows and the second group belong to non-overlapping groups. The device includes multiple nonvolatile memory rows, and a controller receiving a codeword comprising a first codeword portion and a second codeword portion. The controller writing the first codeword portion to portions of nonvolatile memory rows, and writing the second codeword portion to portions of nonvolatile memory rows, wherein the first group of nonvolatile memory rows differs and the second group of nonvolatile memory rows belong to non-overlapping groups, and the first and second groups of memory rows belong to multiple rows. A computer readable medium having stored thereon instructions performing methods described herein.
1. A method for programming codewords having at least two codeword portions, the method comprising: writing different portions of the codewords to at least two groups of nonvolatile memory row portions that belong to non-overlapping groups of nonvolatile memory rows; wherein the writing comprises writing first different portions of the codewords to at least one group of odd nonvolatile memory row portions in a first order; and writing second different portions of the codewords to at least one group of even nonvolatile memory row portions in a second order, the second order differing from the first order.
2. The method of claim 1 , wherein the second order being in an opposite order to the first order.
3. The method of claim 1 , wherein the at least one group of odd nonvolatile memory row portions and the at least one group of even nonvolatile row portions belong to different integrated circuits.
4. The method of claim 1 , wherein the at least one group of odd nonvolatile memory row portions and the at least one group of even nonvolatile row portions belong to different nonvolatile memory erase blocks.
5. A device, comprising: multiple nonvolatile memory rows; and a controller configured to receive a plurality of codewords, and to write different portions of the plurality of codewords to at least two groups of nonvolatile memory row portions that belong to non-overlapping different groups of nonvolatile rows; wherein the controller is configured to: write first different portions of the plurality of codewords to at least one group of odd nonvolatile memory row portions in a first order; and write second different portions of the plurality of codewords to at least one group of even nonvolatile memory row portions in a second order.
6. The device of claim 5 , wherein the second order being in an opposite order to the first order.
7. The device of claim 5 , wherein the at least one group of odd nonvolatile memory row portions and the at least one group of even nonvolatile row portions belong to different integrated circuits.
8. The device of claim 5 , wherein the at least one group of odd nonvolatile memory row portions and the at least one group of even nonvolatile row portions belong to different nonvolatile memory erase blocks.
9. A non-transitory computer readable medium having stored thereon instructions which when executed by a processor cause the processor to perform the method of: receiving a plurality of codewords; and writing different portions of the plurality of codewords to at least two groups of nonvolatile memory row portions that belong to different groups of non-overlapping nonvolatile memory rows; wherein the writing comprises writing different portions of the plurality of codewords to at least one group of odd nonvolatile memory row portions of a first order; and writing different portions of the plurality of codewords to at least one group of even nonvolatile memory row portions of a second order, the second order differing from the first order.
10. The non-transitory computer readable medium of claim 9 , wherein the at least one group of odd nonvolatile memory row portions and the at least one group of even nonvolatile row portions belong to different integrated circuits.
11. The non-transitory computer readable medium of claim 9 , wherein the at least one group of odd nonvolatile memory row portions and the at least one group of even nonvolatile row portions belong to different nonvolatile memory erase blocks.
12. The non-transitory computer readable medium of claim 9 , wherein the second order being in an opposite order to the first order.