Process, temperature, part and setting independent reset pulse encoding and decoding scheme

1. A reset circuit comprising:

first, second, and third counters for receiving a first clock signal and a second clock signal;

a first comparator coupled to an output of the first and second counters;

a second comparator coupled to an output of the second and third counters; and

a reset generator coupled to an output of the first comparator and to an output of the second comparator for generating a reset signal.

2. The reset circuit of claim 1 wherein the reset circuit comprises an integrated circuit.

3. The reset circuit of claim 2 wherein the first clock signal comprises an external clock signal.

4. The reset circuit of claim 2 wherein the second clock signal comprises an internal clock signal.

5. The reset circuit of claim 2 wherein the integrated circuit includes a clock pin for receiving the first clock signal and a data pin for receiving a data signal.

6. The reset circuit of claim 2 wherein the integrated circuit lacks a reset pin.

7. The reset circuit of claim 1 further comprising a divider circuit interposed between the output of the first counter and an input of the first comparator.

8. The reset circuit of claim 1 further comprising a divider circuit interposed between the output of the second counter and an input of the second comparator.

9. The reset circuit of claim 1 further comprising a finite state machine.

10. The reset circuit of claim 9 wherein the finite state machine comprises a calibrate output, a first measurement output, and a second measurement output.

11. The reset circuit of claim 10 wherein the first counter comprises an enable input coupled to the calibrate output of the finite state machine.

12. The reset circuit of claim 10 wherein the second counter comprises an enable input coupled to the first measurement output of the finite state machine.

13. The reset circuit of claim 10 wherein the third counter comprises an enable input coupled to the second measurement output of the finite state machine.

14. The reset circuit of claim 1 wherein the reset signal comprises a reset pulse.

15. A method of generating an internal reset signal for an integrated circuit lacking a reset pin comprising:

calibrating a first clock pulse from an external clock signal;

measuring a second clock pulse from the external clock signal;

measuring a third clock pulse from the external clock signal; and

generating an internal reset signal; and

returning to an idle condition if the calibration of the first clock pulse fails, or if the measurement of the second or third clock pulse is not equal to an expected value.

16. The method of claim 15 wherein the second clock pulse width is about half that of the first clock pulse width, and the third clock pulse width is about half that of the second clock pulse width.

17. A method of generating a reset signal comprising:

calibrating a first clock pulse from a clock signal;

measuring a second clock pulse from the clock signal;

measuring a third clock pulse from the clock signal; and

generating an internal reset signal if the first clock pulse width is longer than a predetermined minimum clock pulse width, if the second clock pulse is within a first expected value range, and if the third clock pulse is within a second expected value range.

18. A method of generating a reset signal for an integrated circuit comprising:

calibrating a first clock pulse from an external signal;

measuring a second clock pulse from the external signal;

measuring a third clock pulse from the external signal; and

generating an internal reset signal if the first clock pulse width is longer than a predetermined minimum clock pulse width, if the second clock pulse is within a first expected value range, and if the third clock pulse is within a second expected value range.