Semiconductor device and method for manufacturing the same

1. A method of manufacturing a semiconductor device, comprising:

forming an element isolation groove in the semiconductor substrate by etching the semiconductor substrate so as to define a plurality of cell active regions in a cell region in the semiconductor substrate by the element isolation groove, and to define a dummy active region in the semiconductor substrate beside the cell region;

forming an element isolation insulating film in the element isolation groove;

etching the element isolation insulating film to lower an upper surface of the element isolation insulating film than the upper surface of the semiconductor substrate;

forming a thermally-oxidized film on a side surface of the element isolation groove after the etching of the element isolation insulating film to make the thermally-oxidized film and the element isolation insulating film into a capacitor dielectric film;

forming an upper electrode over the capacitor dielectric film and a gate electrode of a MOS transistor over the cell active region with a gate insulating film interposed therebetween, the upper electrode constituting a capacitor together with the capacitor dielectric film and the semiconductor substrate; and

implanting an impurity into the semiconductor substrate of the cell active region beside the gate electrode and the dummy active region.

2. The method of manufacturing a semiconductor device according to claim 1 ,

wherein, the capacitor and the MOS transistor function as a one transistor-one capacitor-type memory cell.

3. The method of manufacturing a semiconductor device according to claim 2 , wherein, when forming the element isolation groove, an interval between the cell active regions in an end portion of the cell region and the dummy active region is set smaller than the width of the memory cell.

4. The method of manufacturing a semiconductor device according to claim 2 , wherein, when forming the element isolation groove, the dummy active region is formed in a stripe shape extending in a repeating direction of the memory cell.

5. The method of manufacturing a semiconductor device according to claim 1 , wherein, when forming the element isolation groove, the dummy active region is formed independently from the cell active region.

6. A method of manufacturing a semiconductor device, comprising:

forming an element isolation groove in a semiconductor substrate to define a plurality of active regions in a cell region of the semiconductor substrate;

forming an element isolation insulating film in the element isolation groove;

etching the element isolation insulating film in a portion other than an end portion of the cell region to leave the element isolation insulating film with a first thickness on a bottom surface of the element isolation groove;

etching the element isolation insulating film in the end portion of the cell region to leave the element isolation insulating film with a second thickness on a bottom surface of the element isolation groove, the second thickness being thicker than the first thickness;

forming a well in the semiconductor substrate in the cell region;

forming a thermally-oxidized film on a side surface of the element isolation groove after the element isolation insulating film is left with the first and second thicknesses, to make the thermally-oxidized film and the element isolation insulating film into a capacitor dielectric film;

forming an impurity diffusion region by implanting ions of an impurity having a same conductivity type as that of the well into the semiconductor substrate under the element isolation groove, after the element isolation insulating film is left with the first and second thicknesses; and

forming an upper electrode over the capacitor dielectric film, the upper electrode constituting a capacitor together with the capacitor dielectric film and the semiconductor substrate.

7. The method of manufacturing a semiconductor device according to claim 6 , wherein, when forming the impurity diffusion region, such an energy is employed as an acceleration energy of the ion implantation that a peak of an impurity concentration of the impurity diffusion region is positioned in a bottom surface of the element isolation groove in the end portion of the cell region.

8. The method of manufacturing a semiconductor device according to claim 6 , further comprising:

forming a MOS transistor in a peripheral circuit region of the semiconductor substrate,

wherein, when forming the impurity diffusion region, an impurity diffusion region for adjusting a threshold voltage of the MOS transistor is formed in the peripheral circuit region of the semiconductor substrate.

9. A method of manufacturing a semiconductor device, comprising:

forming an element isolation groove in a semiconductor substrate to define a plurality of active regions in a cell region of the semiconductor substrate;

forming an element isolation insulating film in the element isolation groove;

etching the element isolation insulating film to lower an upper surface of the element isolation insulating film than an upper surface of the semiconductor substrate;

forming a well in the semiconductor substrate in the cell region;

forming a thermally-oxidized film on a side surface of the element isolation groove after the etching of the element isolation insulating film, to make the thermally-oxidized film and the element isolation insulating film into a capacitor dielectric film;

forming a channel stop region by implanting ions of an impurity having the same conductivity type as that of the well into the semiconductor substrate under the element isolation groove after the etching of the element isolation insulating film;

implanting ions of an impurity having the same conductivity type as that of the channel stop region into the semiconductor substrate under the element isolation groove in an end portion of the cell region to increase an impurity concentration of the channel stop region in the end portion; and

forming an upper electrode over the capacitor dielectric film, the upper electrode constituting a capacitor together with the capacitor dielectric film and the semiconductor substrate.

10. The method of manufacturing a semiconductor device according to claim 9 , wherein, when increasing the impurity concentration of the channel stop region, such an energy is employed as an acceleration energy of the ion implantation that a peak of the impurity concentration of the channel stop region in the end portion of the cell region coincides with a bottom surface of the element isolation groove in the end portion.