Memory using tunneling field effect transistors

1. A memory comprising:

a first tunneling field effect transistor including a first drain and a first p+ doped source, the first drain coupled to a first resistive memory element;

a second tunneling field effect transistor including a second drain and a second p+ doped source, the second drain coupled to a second resistive memory element; and

a p+ doped region coupled to the first p+ doped source and the second p+ doped source,

wherein the p+ doped region directly contacts the first p+ doped source.

2. The memory of claim 1 , wherein the first resistive memory element comprises a phase change memory element.

3. The memory of claim 1 , wherein the first resistive memory element comprises one of a conductive bridging memory element, an electrolyte memory element, and a magnetic memory element.

4. The memory of claim 1 , wherein the p+ doped region comprises a ground plate.

5. A memory comprising:

a substrate;

a first tunneling field effect transistor and a second tunneling field effect transistor sharing a p+ doped source;

a first phase change memory element coupled to an n+ doped drain of the first tunneling field effect transistor;

a second phase change memory element coupled to an n+ doped drain of the second tunneling field effect transistor; and

a p+ region within the substrate coupled to the source to provide a source node.

6. The memory of claim 5 , further comprising:

a bit line coupled to the first phase change memory element; and

a word line coupled to a gate of the first tunneling field effect transistor.

7. A memory comprising:

a substrate;

a first tunneling field effect transistor and a second tunneling field effect transistor sharing a p+ doped source;

a first phase change memory element coupled to an n+ doped drain of the first tunneling field effect transistor;

a second phase change memory element coupled to an n+ doped drain of the second tunneling field effect transistor; and

a p+ region within the substrate coupled to the source to provide a source node,

wherein the p+ region directly contacts the source.

8. The memory of claim 7 , further comprising:

a bit line coupled to the first phase change memory element; and

a word line coupled to a gate of the first tunneling field effect transistor.

9. A memory comprising:

a first tunneling field effect transistor including a first drain and a first doped source, the first drain coupled to a first resistive memory element;

a second tunneling field effect transistor including a second drain and a second doped source, the second drain coupled to a second resistive memory element; and

a doped region coupled to the first doped source and the second doped source,

wherein the doped region directly contacts the first doped source.