ON-CHIP BUS
This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting multiple outstanding transactions with a plurality of on-chip devices over the on-chip bus wherein each on-chip device transmits all of its data signals across the on-chip bus in the form of packets. The on-chip bus includes at least one bus register, and each of the multiple on-chip devices includes at least one device register. The on-chip bus can provide top level register to register communications between the device register and the bus register. In one version, the on-chip bus is a distributed packet on-chip (DPO) bus.
1 . An on-chip system comprising:
a plurality of on-chip devices including one or more hardware logic portions configured to implement at least a portion of an application program;
an on-chip bus configured to enable communications between the on-chip devices to run the application program using a combination of the on-chip devices; and
a root collector device configured to facilitate packet communication to and from the on-chip devices via the on-chip bus using addressable packets.
2 . The on-chip system as described in claim 1 , wherein using addressable packets comprises formatting data signals, grant signals, and request signals in a common form of addressable packets.
3 . The on-chip system as described in claim 1 , wherein the on-chip bus includes a plurality of device nodes associated with respective ones of the plurality of on-chip devices.
4 . The on-chip system as described in claim 1 , wherein each of the plurality of on-chip devices is associated with a device node configured to communicate with the root collector device.
5 . The on-chip system as described in claim 1 , wherein the root collector device is implemented as a component of the on-chip bus.
6 . The on-chip system as described in claim 1 , wherein the on-chip bus is configured to make available multiple selectable bus topologies via the on-chip bus.
7 . The on-chip system as described in claim 6 , wherein the multiple selectable bus topologies made available via the on-chip bus include a point-to-point topology and a ring topology.
8 . The on-chip system as described in claim 1 , further comprising one or more bridge devices configured to connect at least two independent bus topologies into which the plurality of on-chip of devices are arranged and which together form the on-chip bus.
9 . The on-chip system as described in claim 1 , wherein the on-chip system is integrated with a computing device.
10 . The on-chip system as described in claim 1 , wherein the on-chip system comprises at least a portion of a portable communication device.
11 . The on-chip system as described in claim 1 , further comprising one or more processors, one or more computer-readable storage media, and one or more input/output circuits.
12 . A computing device comprising:
one or more processors;
a plurality of on-chip devices including one or more hardware logic portions configured to implement at least a portion of an application program;
an on-chip bus configured to enable communications between the on-chip devices to run the application program using a combination of the on-chip devices; and
a root collector device configured to facilitate packet communication to and from the on-chip devices via the on-chip bus using addressable packets.
13 . The computing device as described in claim 12 , further comprising at least one bridge device to connect two independent bus topologies into which the plurality of on-chip devices are arranged to form the on-chip bus.
14 . The computing device as described in claim 12 , wherein each of the plurality of on-chip devices is configured to implement a distinct portion of the application program.
15 . The computing device as described in claim 12 , wherein the root collector device includes a collector node communicably connected with multiple device nodes each associated respectively with one of the plurality of on-chip devices to enable communications via the on-chip bus using the addressable packets.
16 . The computing device as described in claim 12 , wherein the on-chip bus is configured to enable, via a combination of software, firmware, or hardware, selectable arrangement of the plurality of on-chip devices into one or more independent bus topologies such that the plurality of on-chip devices are arrangable into different topologies at different times.
17 . A portable communication device comprising:
one or more wireless communication components;
a plurality of on-chip devices including one or more hardware logic portions configured to implement at least a portion of an application program;
an on-chip bus configured to enable selectable arrangement of the plurality of on-chip devices into different bus topologies and communications between the on-chip devices to run the application program using a combination of the on-chip devices; and
a root collector device configured to facilitate packet communication to and from the on-chip devices via the on-chip bus using addressable packets.
18 . The portable communication device as described in claim 17 , wherein the on-chip bus includes at least two independent bus topologies into which the plurality of on-chip devices are arranged.
19 . The portable communication device as described in claim 18 , further comprising at least one bridge device to connect the two independent bus topologies to form the on-chip bus.
20 . The portable communication device as described in claim 17 , wherein the on-chip bus includes a plurality of device nodes associated with respective ones of the plurality of on-chip devices.