Semiconductor device having gate insulating film including high dielectric material
View Patent ↗A semiconductor device includes: a first MIS transistor of a first conductivity type having a first active region as a region of a semiconductor substrate surrounded by an element isolation region formed in an upper portion of the semiconductor substrate, a first gate insulating film having a first high dielectric film formed on the first active region, and a first gate electrode formed on the first gate insulating film; and a resistance element having a second high dielectric film formed on the element isolation region and a resistance layer made of silicon formed on the second high dielectric film. The first high dielectric film and the second high dielectric film include the same high dielectric material, and the first high dielectric film includes a first adjustment metal, but the second high dielectric film does not include the first adjustment metal.
1. A semiconductor device, comprising:
a first metal insulator semiconductor (MIS) transistor of a first conductivity type having a first active region as a region of a semiconductor substrate surrounded by an element isolation region formed in an upper portion of the semiconductor substrate, a first gate insulating film having a first high dielectric film formed on the first active region, and a first gate electrode formed on the first gate insulating film; and
a resistance element having a second high dielectric film formed on the element isolation region and a resistance layer made of a first silicon film formed on the second high dielectric film,
wherein the first high dielectric film and the second high dielectric film include a same high dielectric material, and
the first high dielectric film includes a first adjustment metal, but the second high dielectric film does not include the first adjustment metal,
the semiconductor device further includes a second MIS transistor of a second conductivity type having a second active region as a region of the semiconductor substrate surrounded by the element isolation region formed in an upper portion of the semiconductor substrate, a second gate insulating film having a third high dielectric film formed on the second active region, and a second gate electrode formed on the second gate insulating film,
the third high dielectric film includes the same high dielectric material as the first high dielectric film and the second high dielectric film, and includes a second adjustment metal, but does not include the first adjustment metal, and
the second gate insulating film includes a second underlying insulating film formed on the second active region, the third high dielectric film formed on the second underlying insulating film, and a second adjustment metal-containing film containing the second adjustment metal formed on the third high dielectric film.
2. The semiconductor device of claim 1 , wherein the first gate electrode is formed on, and in contact with, the first high dielectric film of the first gate insulating film.
3. The semiconductor device of claim 1 , wherein the resistance layer is formed only above the element isolation region.
4. The semiconductor device of claim 1 , further comprising:
a protective insulating film formed on the resistance layer,
wherein the protective insulating film is not formed above the first active region including the first gate electrode.
5. The semiconductor device of claim 1 , wherein the first gate insulating film includes a first underlying insulating film formed on the first active region and the first high dielectric film formed on the first underlying insulating film.
6. The semiconductor device of claim 1 , further comprising:
first sidewall insulating films formed on the side faces of the first gate insulating film and the first gate electrode; and
second sidewall insulating films formed on the side faces of the second high dielectric film and the resistance layer.
7. The semiconductor device of claim 1 , further comprising:
a silicide layer formed on the first gate electrode.
8. The semiconductor device of claim 1 , wherein the first adjustment metal is a metal with which silicon grows abnormally.
9. The semiconductor device of claim 1 , wherein the first MIS transistor is an n-type MIS transistor,
the resistance layer is made of n-type silicon, and
the first adjustment metal is lanthanum.
10. The semiconductor device of claim 1 , wherein the second high dielectric film includes the second adjustment metal.
11. The semiconductor device of claim 1 , wherein the second gate electrode includes a second metal film formed on the second gate insulating film and a third silicon film formed on the second metal film.
12. The semiconductor device of claim 1 , wherein the second MIS transistor is a p-type MIS transistor, and
the second adjustment metal is aluminum.
13. The semiconductor device of claim 1 , wherein the second high dielectric film is formed on the element isolation region via a third underlying insulating film.
14. The semiconductor device of claim 1 , wherein the second high dielectric film is formed on, and in contact with, the element isolation region.