Multi-speed burst mode serializer/de-serializer
View Patent ↗A multi-speed burst mode serializer/de-serializer (SerDes) is configurable and can operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds. These various modes of operation can enable a single SerDes design to apply to a variety of speeds and network configurations (e.g., point-to-point or point-to-multipoint). In one example, the design can be initially configured for operation with a single ONT or a network of ONTs at a single speed, or can be dynamically configured during operation for use with a network of ONTs operating at different speeds.
1. A multi-speed serializer/de-serializer transceiver, comprising:
a clock recovery module that is configurable to switch between a plurality of modes based on a speed indication for a received signal, wherein a first mode in said plurality of modes enables clock recovery from a signal received from a first network unit at a first speed, and a second mode in said plurality of modes enables clock recovery from a signal received from a second network unit at a second speed different from said first speed; and
a non-volatile memory that stores a first parameter for the configuration of said clock recovery module in a first mode, and a second parameter for the configuration of said clock recovery module in a second mode.
2. The multi-speed serializer/de-serializer transceiver of claim 1 , wherein said clock recovery module includes a phase locked loop.
3. The multi-speed serializer/de-serializer transceiver of claim 1 , wherein said clock recovery module includes a delay locked loop.
4. The multi-speed serializer/de-serializer transceiver of claim 1 , wherein communication from said first network unit and said second network unit are received on different time slots.
5. The multi-speed serializer/de-serializer transceiver of claim 1 , wherein a selected mode of said clock recovery module is based on a speed indication of a received signal.
6. The multi-speed serializer/de-serializer transceiver of claim 5 , is provided through one or more external pins to the multi-speed serializer/de-serializer transceiver.
7. The multi-speed serializer/de-serializer transceiver of claim 5 , wherein said speed indication is provided through an EPROM.
8. The multi-speed serializer/de-serializer transceiver of claim 5 , wherein said speed indication is provided through in-band communication to the multi-speed serializer/de-serializer transceiver.
9. A multi-speed serializer/de-serializer, comprising:
a clock recovery module that is configurable to operate in a plurality of modes, wherein a first of said plurality of modes is capable of recovering a clock from received signals generated by a first network unit at a first speed, and a second of said plurality of modes is capable of recovering a clock from received signals generated by a second network unit at a second speed different from said first speed,
wherein said clock recovery module is configured to switch between said plurality of modes based on a speed indication for said received signals.
10. The multi-speed serializer/de-serializer of claim 9 , further comprising a non-volatile memory that stores parameters for said first mode and said second mode.
11. The multi-speed serializer/de-serializer of claim 10 , wherein said parameters are values for a clock multiplier/divider.
12. The multi-speed serializer/de-serializer of claim 9 , wherein said clock recovery module includes a phase locked loop.
13. The multi-speed serializer/de-serializer of claim 9 , wherein said clock recovery module includes a delay locked loop.
14. The multi-speed serializer/de-serializer of claim 9 , wherein said speed indication is provided through one or more external pins to the multi-speed serializer/de-serializer transceiver.
15. The multi-speed serializer/de-serializer of claim 9 , wherein said speed indication is provided through an EPROM.
16. The multi-speed serializer/de-serializer of claim 9 , wherein said speed indication is provided through in-band communication to the multi-speed serializer/de-serializer transceiver.
17. A multi-speed serializer/de-serializer method in a receiving system having a clock recovery module that is configured in a first operating mode that recovers a clock from a first signal generated by a first network unit operating at a first operating speed, comprising:
retrieving one or more parameters stored in a non-volatile memory based on an indication of receipt of a second signal generated by a second network unit operating at a second operating speed different from said first operating speed; and
reconfiguring, using said retrieved parameters, said clock recovery module to change from said first operating mode to a second operating mode designed to recover a clock from said second signal.
18. The method of claim 17 , wherein said reconfiguring comprises configuring a phase locked loop.
19. The method of claim 17 , wherein said reconfiguring comprises configuring a delay locked loop.
20. The method of claim 17 , wherein said reconfiguring comprises configuring a clock multiplier/divider.