Semiconductor device and display device
A semiconductor device can easily reduce a leak current which flows when a reversely-staggered-type TFT element in which an active layer is made of polycrystalline semiconductor is turned off. The semiconductor device includes a reversely-staggered-type TFT element in which a semiconductor layer, a source electrode and a drain electrode are arranged on a surface of an insulation film, and a portion of the source electrode and a portion of the drain electrode respectively get over the semiconductor layer. The active layer of the semiconductor layer is mainly made of polycrystalline semiconductor constituted of strip-shaped crystals elongated in the channel length direction of the TFT element, and is configured in a plan view such that the source electrode and the drain electrode are respectively pulled out from positions above the active layer in the channel width direction of the TFT element and in the directions opposite to each other, and the source electrode intersects with only one side out of two sides of the active layer which extend in the channel length direction, and the drain electrode intersects with only another side out of two sides of the active layer which extend in the channel length direction.
1 . A semiconductor device having a TFT element in which a gate electrode, an insulation film, a semiconductor layer, a source electrode and a drain electrode are stacked on a surface of an insulation substrate in this order, and
the semiconductor layer, the source electrode and the drain electrode are arranged on a surface of the insulation film, and a portion of the source electrode and a portion of the drain electrode respectively get over the semiconductor layer, wherein
the semiconductor layer includes an active layer made of polycrystalline semiconductor, a first contact layer interposed between the active layer and the source electrode, and a second contact layer interposed between the active layer and the drain electrode,
the TFT element is configured in a plan view such that the source electrode and the drain electrode are respectively pulled out from positions above the active layer in the channel width direction of the TFT element and in the directions opposite to each other, and
the TFT element is configured in a plan view such that the source electrode intersects with only one side out of two sides of the active layer which extend in the channel length direction, and the drain electrode intersects with only another side out of two sides of the active layer which extend in the channel length direction.
2 . A semiconductor device having a TFT element in which a gate electrode, an insulation film, a semiconductor layer, a source electrode and a drain electrode are stacked on a surface of an insulation substrate in this order, and
the semiconductor layer, the source electrode and the drain electrode are arranged on a surface of the insulation film, and a portion of the source electrode and a portion of the drain electrode respectively get over the semiconductor layer, wherein
the semiconductor layer includes an active layer, a first contact layer interposed between the active layer and the source electrode, and a second contact layer interposed between the active layer and the drain electrode,
the active layer includes a polycrystalline semiconductor layer and an amorphous semiconductor layer which is stacked on the polycrystalline semiconductor layer as viewed from the insulation substrate,
the TFT element is configured in a plan view such that the source electrode and the drain electrode are respectively pulled out from positions above the active layer in the channel width direction of the TFT element and in the directions opposite to each other, and
the TFT element is configured in a plan view such that the source electrode intersects with only one side out of two sides of the active layer which extend in the channel length direction, and the drain electrode intersects with only another side out of two sides of the active layer which extend in the channel length direction.
3 . A semiconductor device according to claim 2 , wherein the first contact layer and the second contact layer are respectively arranged only on an upper portion of the active layer as viewed from the insulation substrate, and
the source electrode and an etching end surface of the active layer are brought into direct contact with each other, and the drain electrode and an etching end surface of the active layer are brought into direct contact with each other.
4 . A display device including an insulation substrate, a display region which is formed of a mass of a plurality of pixel regions and one or a plurality of integrated circuit regions arranged outside the display region, wherein
a TFT element is arranged in the integrated circuit region,
the TFT element is formed by stacking a gate electrode, an insulation film, a semiconductor layer, a source electrode and a drain electrode on a surface of an insulation substrate in this order,
the semiconductor layer, the source electrode and the drain electrode are arranged on a surface of the insulation film, and a portion of the source electrode and a portion of the drain electrode respectively get over the semiconductor layer,
the semiconductor layer includes an active layer made of polycrystalline semiconductor, a first contact layer interposed between the active layer and the source electrode, and a second contact layer interposed between the active layer and the drain electrode,
the TFT element is configured in a plan view such that the source electrode and the drain electrode are respectively pulled out from positions above the active layer in the channel width direction of the TFT element and in the directions opposite to each other, and
the TFT element is configured in a plan view such that the source electrode intersects with only one side out of two sides of the active layer which extend in the channel length direction, and the drain electrode intersects with only another side out of two sides of the active layer which extend in the channel length direction.
5 . A display device including an insulation substrate, a display region which is formed of a mass of a plurality of pixel regions and one or a plurality of integrated circuit regions arranged outside the display region, wherein
a TFT element is arranged in the integrated circuit region,
the TFT element is formed by stacking a gate electrode, an insulation film, a semiconductor layer, a source electrode and a drain electrode on a surface of an insulation substrate in this order, and
the semiconductor layer, the source electrode and the drain electrode are arranged on a surface of the insulation film, and a portion of the source electrode and a portion of the drain electrode respectively get over the semiconductor layer,
the semiconductor layer includes an active layer, a first contact layer interposed between the active layer and the source electrode, and a second contact layer interposed between the active layer and the drain electrode,
the active layer includes a polycrystalline semiconductor layer and an amorphous semiconductor layer which is stacked on the polycrystalline semiconductor layer as viewed from the insulation substrate, and
the TFT element is configured in a plan view such that the source electrode and the drain electrode are respectively pulled out from positions above the active layer in the channel width direction of the TFT element and in the directions opposite to each other, and
the TFT element is configured in a plan view such that the source electrode intersects with only one side out of two sides of the active layer which extend in the channel length direction, and the drain electrode intersects with only another side out of two sides of the active layer which extend in the channel length direction.
6 . A display device according to claim 5 , wherein in each one of the plurality of pixel regions formed in the display region, a switching element and a pixel electrode are arranged.
7 . A display device according to claim 6 , wherein the switching element is a MISFET having an amorphous semiconductor layer.
8 . A display device according to claim 6 , wherein the switching element is a MISFET having a polycrystalline semiconductor layer.
9 . A display device according to claim 5 , wherein the plurality of TFT elements and the plurality of pixel electrodes are arranged in the display region in a matrix array.
10 . A display device according to any one of claim 9 , wherein the first contact layer and the second contact layer are respectively arranged only on an upper portion of the active layer as viewed from the insulation substrate, and
the source electrode and an etching end surface of the active layer are brought into direct contact with each other, and the drain electrode and an etching end surface of the active layer are brought into direct contact with each other.