Liquid crystal display device with decreased power consumption
View Patent ↗The present invention relates to enhancing low power consumption of a display device having a SRAM. The display device includes a drive circuit receiving video data; video lines connected the drive circuit; and pixels connected to the video signals. The drive circuit includes a memory storing the video data in memory cells. Each memory cell includes a first inverter with input and output terminals connected to first and second nodes, respectively. A second inverter has output and input terminals connected to the first and second nodes, respectively. A First and second transistors between a first data line and the first node each have a control terminal connected to a first word line or a third word line, respectively. Third and fourth transistors between a second data line and the second node each have a control terminal connected to a second word line or a fourth word line, respectively.
1. A display device comprising:
a drive circuit supplying a video signal corresponding to a video data;
a plurality of video lines electrically connected with the drive circuit;
a plurality of pixels being supplied the video signal through the video lines;
the drive circuit including a static random access memory, a video signal decode circuit, a level shift circuit, an amplifier and a clocked inverter circuit;
wherein
the static random access memory stores the video data,
the video signal decode circuit decodes the video data to video signal,
the amplifier output the video signal to the video line,
the clocked inverter circuit inputs one bit of the video data and outputs the video signal to the video line when the amplifier stops outputting the video signal,
the clocked inverter circuit is stopped by a clock signal, and
the level shift circuit stops level shift operation of bits of the video data except the bit which inputs into the clocked inverter circuit when the amplifier stops outputting the video signal.
2. A display device according to claim 1 , wherein the amplifier stops outputting the video signal in the partial display mode.
3. A display device according to claim 1 , wherein the clocked inverter circuit input a minimum gray scale voltage or maximum gray scale voltage.
4. A display device comprising:
a drive circuit supplying a gray scale voltage corresponding to a video data;
a plurality of video lines electrically connected with the drive circuit;
a plurality of pixels being supplied the gray scale voltage through the video lines;
the drive circuit including a static random access memory, a decode circuit, an amplifier, a level shift circuit and a clocked inverter circuit;
wherein
the static random access memory stores the video data,
the decode circuit decodes the video data to gray scale voltage,
the amplifier output the gray scale voltage to the video line,
the clocked inverter circuit inputs one bit of the video data and outputs one of the gray scale voltage to the video line in a partial display mode,
the clocked inverter circuit is stopped by a clock signal, and
the level shift circuit stops level shift operation of bits of the video data except the bit which inputs into the clocked inverter circuit when the amplifier stops outputting the video signal.
5. A display device according to claim 4 , wherein the amplifier stops in the partial display mode.
6. A display device according to claim 5 , wherein the clocked inverter circuit input a minimum gray scale voltage or maximum gray scale voltage.