Semiconductor device and multilayer semiconductor device
View Patent ↗Disclosed herein is a semiconductor device including: an input terminal receiving, if a preceding-stage semiconductor device is layered on a predetermined one of an upper layer and a lower layer, a bit train outputted from the preceding-stage semiconductor device; a semiconductor device identifier hold block holding a semiconductor device identifier for uniquely identifying the semiconductor device; a semiconductor device identifier computation block executing computation by using the semiconductor device identifier to update the semiconductor device identifier held in the semiconductor device identifier hold block according to a result of the computation; a control block once holding data of a bit train entered from the input terminal to control updating of the semiconductor device identifier executed by the semiconductor device identifier computation block based on the held data; and an output terminal outputting the bit train held in the control block to a succeeding-stage semiconductor device layered on another layer.
1. A semiconductor device comprising:
an input terminal configured, if a preceding-stage semiconductor device is layered on a predetermined one of an upper layer and a lower layer, to receive a bit train outputted from said preceding-stage semiconductor device;
a chip identifier hold block configured to hold a chip identifier for uniquely identifying said semiconductor device;
a chip identifier computation block configured to execute computation by use of said chip identifier to update said chip identifier held in said chip identifier hold block in accordance with a result of the computation;
a control block configured to once hold data of a bit train entered from said input terminal to control updating of said chip identifier executed by said chip identifier computation block on the basis of said held data; and
an output terminal configured to output said bit train held in said control block to a succeeding-stage semiconductor device layered on another layer.
2. The semiconductor device according to claim 1 , wherein said control block controls the execution of the updating of said chip identifier in accordance with said held data.
3. The semiconductor device according to claim 2 , wherein, if a value of said held data is a predetermined prohibition instruction value, then said control block prohibits the updating of said chip identifier and, if a value of said held data is not said predetermined prohibition instruction value, then allows the updating of said chip identifier.
4. The semiconductor device according to claim 1 , wherein said control block holds and sequentially shifts a bit train of semiconductor device associated data indicating predetermined contents of information associated with a semiconductor device in which said information is entered and executes the updating of said chip identifier in accordance with a timing at which said held semiconductor device associated data have all been shifted out.
5. The semiconductor device according to claim 4 , wherein said control block executes the updating of said chip identifier in accordance with a timing at which a shift count according to a bit length of said semiconductor device associated data based on a fixed length has been counted.
6. The semiconductor device according to claim 4 , wherein said semiconductor device associated data is made up of a real data part based on a given data length and a data length part based on a fixed length, and
said control block executes the updating of said semiconductor identifier in accordance with a timing at which a bit train having a bit length indicated by said held data length part has been shifted out.
7. The semiconductor device according to claim 1 , wherein said control block executes the updating of said chip identifier in accordance with said computation result obtained by adding a constant value to said chip identifier.
8. The semiconductor device according to claim 1 , wherein said control block executes the updating of said chip identifier in accordance with said computation result obtained by use of said held data and said chip identifier.
9. The semiconductor device according to claim 8 , wherein said control block gets addition value data to be added to said chip identifier from said input terminal to hold the obtained addition value data and executes the updating of said chip identifier in accordance with said computation result obtained by adding a value of said held addition value data to said chip identifier.
10. The semiconductor device according to claim 9 , wherein the value of said addition value data indicates the number of storage blocks of a corresponding semiconductor device.
11. The semiconductor device according to claim 3 , further comprising:
a fixed value input block through which bits based on a fixed value are entered into said control block if no bit train is entered from said input terminal, said prohibition instruction value being a value obtained when each bit of said held data is said fixed value.
12. The semiconductor device according to claim 11 , wherein said fixed value input block is a pullup resistor inserted between a signal line based on positive supply voltage and an input of said control block.
13. The semiconductor device according to claim 11 , wherein said fixed value input block is a pulldown resistor inserted between ground signal line and an input of said control block.
14. A multilayer semiconductor device comprising:
a plurality of layered semiconductor devices; and
a storage device that is layered on said plurality of layered semiconductor devices;
wherein each of said plurality of layered semiconductor devices has
an input terminal configured, by being connected to an output terminal of another semiconductor device layered on one of an upper layer and a lower layer, to receive a bit train outputted from said connected output terminal,
a chip identifier hold block configured to hold a chip identifier for uniquely identifying said semiconductor device,
a chip identifier computation block configured to execute computation by use of said chip identifier to update said chip identifier held in said chip identifier hold block in accordance with a result of the computation,
a control block configured to once hold data of a bit train inputted from said input terminal to control the updating of said chip identifier executed by said chip identifier computation block on the basis of said held data, said controlling block receiving a bit train of semiconductor device associated data indicative of contents of predetermined information associated with a semiconductor device from said input terminal, and
an output terminal configured, by being connected to an input terminal of still another semiconductor device layered on another layer, to output a bit train held in said control block to said connected input terminal, and
said storage device has a semiconductor device associated data storage block configured to receive a bit train outputted from said output terminal of a final stage semiconductor device in said layered semiconductor device to store semiconductor device associated data in said received bit train.
15. A multilayer semiconductor device comprising:
a plurality of layered semiconductor devices;
wherein each of said plurality of semiconductor devices has
an input terminal configured, by being connected to an output terminal of another semiconductor device layered on one of an upper layer and a lower layer, to receive a bit train outputted from said connected output terminal,
a chip identifier hold block configured to hold a chip identifier for uniquely identifying said semiconductor device,
a chip identifier computation block configured to execute computation by use of said chip identifier to update said chip identifier held in said chip identifier hold block in accordance with a result of the computation,
a control block configured to once hold data of a bit train inputted from said input terminal to control the updating of said chip identifier executed by said chip identifier computation block on the basis of said held data and hold semiconductor device associated data indicating contents of predetermined information associated with a semiconductor device as an initial value, and
an output terminal configured, by being connected to an input terminal of another semiconductor device layered on another layer, to output a bit train held in said control block to said connected input terminal.