Liquid crystal display device, driving method for liquid crystal display devices, and inspection method for liquid crystal display devices
View Patent ↗Using technology which uses a single shift register and simultaneously generates multiple pulses, this invention is a liquid crystal display device which rapidly drives data lines. It is possible to increase the frequency of the shift register output signal without changing the frequency of the shift register operation clock. If the shift register output signals, by means of analog switches, are used to determine the video signal sampling timing, high speed data line driving can be realized. Additionally, if the output signals of the shift register mentioned above are used to determine the video signal latch timing in a digital driver, high speed latching of the video signal can be realized. Consequently, even if the driving circuits of the liquid crystal display matrix are composed of TFTs, high speed operation of the driving circuits is possible without increasing power consumption. The shift register can also be used to inspect the electrical characteristics of the data lines and analog switches.
1. A driving circuit, comprising:
a plurality of switches including N switch groups each of which includes a plurality of M switches, two switches of the plurality of M switches in each of the N switch groups being adjacent to each other, the N being a natural number that is more than 1, the M being a natural number that is more than 1;
a plurality of video signal lines transmitting multiplexed video signals to the plurality of M switches of all of the N switch groups, one of the plurality of video signal lines electrically connecting to the plurality of M switches of one of the N switch groups;
a plurality of timing signals lines transmitting timing signals to the plurality of M switches; and
N of the plurality of switches corresponding to the timing signals being simultaneously driven, and n, n+M, . . . , n+(N−1)×Mth ones of signals for N of the plurality of video signal lines within the multiplexed video signals being outputted to the corresponding video signal line, the n being a natural number, and at least one switch of the plurality of switches except for the N of the plurality of switches being disposed between one of the N of the plurality of switches and another of the N of the plurality of switches.
2. The driving circuit according to claim 1 , each of the plurality of switches of the N switch groups being an analog switch.
3. The driving circuit according to claim 1 , a number of the plurality of video signal lines being N, each of the N of the plurality of video signal lines being outputted from different groups of the N switch groups.
4. The driving circuit according to claim 1 , further comprising:
gate circuits providing a plurality of gate signals to the plurality of switches of all of the N switch groups, the gate circuits inputting the timing signals that are outputted from the shift register.
5. The driving circuit according to claim 4 , the gate circuits including a plurality of NAND gates, each NAND gate of the plurality of NAND gates inputting two of the timing signals from the shift register, and each NAND gate of the plurality of NAND gates outputting one of the plurality of gate signals to one of the switches.
6. The driving circuit according to claim 4 , the gate circuits including a plurality of XOR gates, each XOR gate of the plurality of XOR gates inputting two of the timing signals from the shift register, and each XOR gate of the plurality of XOR gates outputting one of the plurality of gate signals to one of the switches.
7. The driving circuit according to claim 4 , further comprising:
an output enable signal line that provides an output enable signal, the gate circuits including a plurality of NAND gates, each NAND gate of the plurality of NAND gates inputting one of the timing signals from the shift register and the output enable signal, and each NAND gate of the plurality of NAND gates outputting one of the plurality of gate signals to one of the switches.
8. An active matrix substrate comprising:
a plurality of scan lines;
a plurality of data lines crossing the plurality of scan lines; and
the driving circuit according to claim 1 , the plurality of switches of all of the N switch groups electrically connecting the plurality of data lines.
9. A display device comprising:
a plurality of scan lines;
a plurality of data lines crossing the plurality of scan lines; and
the driving circuit according to claim 1 , the plurality of switches of all of the N switch groups electrically connecting the plurality of data lines.
10. A driving circuit comprising:
a plurality of switches including N of the plurality of switches outputting N output signals simultaneously, at least one switch of the plurality of switches except for the N of the plurality of switches that outputs a signal at a different time from the N of the plurality of switches being disposed between one of the N of the plurality of switches and another of the N of the plurality of switches, the N being a natural number that is more than 1;
a plurality of video signal lines providing multiplexed video signals to the plurality of switches;
a plurality of timing signals lines transmitting timing signals to the plurality of switches; and
the N of the plurality of switches corresponding to the timing signals being simultaneously driven, and n, n+M, . . . , n+(N−1)×Mth ones of signals for N of the plurality of video signal lines within the multiplexed video signals being outputted to the corresponding video signal line, the M being a natural number that is more than 1, the n being a natural number.
11. A driving circuit, comprising:
a plurality of switches that is divided into a first group and a second group, each of which includes a plurality of M switches, one switch of the first group and one switch of the second group transmitting output signals simultaneously, at least one of the plurality of switches transmitting output signals at a different time from the one switch of the first group and the one switch of the second group being disposed between the one switch of the first group and the one switch of the second group, the M being a natural number that is more than 1;
a plurality of video signal lines providing multiplexed video signals to the plurality of switches;
a plurality of timing signals lines transmitting timing signals to the plurality of M switches; and
N of the plurality of switches corresponding to the timing signals being simultaneously driven, and n, n+Mth ones of signals for N of the plurality of video signal lines within the multiplexed video signals being outputted to the corresponding video signal line, the n being a natural number.
12. A driving circuit, comprising:
a D/A converter that converts a plurality of digital video signals into a plurality of analog video signals;
N circuit groups each of which includes a plurality of M latch circuits, two of the latches of the M latch circuits in each N circuit group being adjacent to each other, a plurality of latch circuits of all of the N circuit groups transmitting the plurality of digital video signals to the D/A converter, the N being a natural number that is more than 1, the M being a natural number that is more than 1;
a plurality of video signal lines transmitting multiplexed video signals to the plurality of latch circuits of all of the N circuit groups, one of the plurality of video signal lines electrically connecting to the M latch circuits of a circuit group;
a plurality of timing signals lines transmitting timing signals to the plurality of M switches; and
N of the plurality of switches corresponding to the timing signals being simultaneously driven, and n, n+M, . . . , n+(N−1)×Mth ones of signals for N of the plurality of video signal lines within the multiplexed video signals being outputted to the corresponding video signal line, the n being a natural number.
13. A driving circuit, comprising:
a D/A converter that converts a plurality of digital video signals into a plurality of analog video signals;
a plurality of first latch circuits transmitting the plurality of digital video signals to the D/A converter;
N circuit groups each of which includes a plurality of M second latch circuits, two of the plurality of M second latch circuits of each N circuit group being adjacent to each other, a plurality of second latch circuits of all of the N circuit groups transmitting the plurality of digital video signals to the D/A converter, the N being a natural number that is more than 1, the M being a natural number that is more than 1;
a plurality of video signal lines transmitting multiplexed video signals to the plurality of second latch circuits of all of the N circuit groups, one of the plurality of video signal lines electrically connecting to the M second latch circuits;
a plurality of timing signals lines transmitting timing signals to the plurality of M switches; and
N of the plurality of switches corresponding to the timing signals being simultaneously driven, and n, n+M, . . . , n+(N−1)×Mth ones of signals for N of the plurality of video signal lines within the multiplexed video signals being outputted to the corresponding video signal line, the n being a natural number.