Method, system and medium for analog encryption in a flash memory
A system and method for analog encryption and decryption. A threshold level encryption key stream is generated and a programming level for each bit of a cipher data stream, with each bit having a one or zero state, is determined, where a threshold for distinguishing between the one or zero state for each bit varies based on a corresponding entry in the threshold level encryption key steam. Each bit of the cipher data stream in a cell of a memory is programmed based on the programming level.
1. A method performed by a memory controller, comprising:
performing a first encryption function on an input data stream to generate a cipher data bit stream;
performing a second encryption function to generate a threshold level encryption key stream, wherein each value in the threshold level encryption key stream corresponds to at least one bit of the cipher data bit stream;
and programming the cipher data bit stream into a memory based on the corresponding values of the threshold level encryption key stream;
wherein the programming the cipher data bit stream into a memory comprises programming the cipher data bit stream into the memory using an incremental stepped pulse programming (ISPP) step having a value based on the corresponding values of the threshold level encryption key stream.
2. The method of claim 1 , wherein programming the cipher data bit stream into a memory based on the corresponding values of the threshold level encryption key stream comprises: determining a programming threshold for each bit in the cipher data bit stream based at least on the corresponding threshold level encryption key stream;
and programming the cipher data bit stream into a memory using the determined programming thresholds corresponding thereto.
3. The method of claim 2 , wherein the number of possible values of the threshold level encryption key stream is greater than the number of possible values of the cipher data bit stream.
4. The method of claim 3 , wherein each value of the threshold level encryption key stream comprises two binary bits, and wherein determining the programming threshold for each bit in the cipher data bit stream comprises selecting one of up to four programming threshold voltage levels based at least on the corresponding threshold level encryption key stream.
5. The method of claim 3 , wherein each value of the threshold level encryption key stream comprises three binary bits, and wherein determining the programming threshold for each bit in the cipher data bit stream comprises selecting one of up to eight programming threshold voltage levels based at least on the corresponding threshold level encryption key stream.
6. The method of claim 3 , wherein each value of the threshold level encryption key stream comprises four binary bits, and wherein determining the programming threshold for each bit in the cipher data bit stream comprises selecting one of up to sixteen programming threshold voltage levels based at least on the corresponding threshold level encryption key stream.
7. The method of claim 3 , wherein each value of the threshold level encryption key stream comprises five binary bits, and wherein determining the programming threshold for each bit in the cipher data bit stream comprises selecting one of up to thirty two programming threshold voltage levels based at least on the corresponding threshold level encryption key stream.
8. The method of claim 2 , wherein programming the cipher data bit stream into the memory using the determined programming thresholds comprises simultaneously storing a page of cipher data bit stream values into a page of memory.
9. The method of claim 8 , comprising simultaneously programming a plurality of cells in the page of memory with a corresponding value of the cipher data bit stream by: performing a coarse programming operation using a first incremental stepped pulse programming (ISPP) parameter; and if the voltage level of the cell after the coarse programming operation is between two desired voltage distribution lobes, then performing a fine programming operation to program the using a second ISPP parameter, wherein the first ISPP parameter is greater than the second ISPP parameter.
10. The method of claim 1 , wherein programming the cipher data bit stream into a memory based on the corresponding values of the threshold level encryption key stream comprises: for a bit of the cipher data bit stream having a logical 0 value, programming a corresponding memory cell to one of a first plurality of voltage levels, and for a bit of the cipher data bit stream having a logical 1 value, programming a corresponding memory cell to one of a second plurality of voltage levels, wherein the first and second plurality of voltage levels are determined by the threshold level encryption key stream value corresponding to the bit of the cipher data bit stream.
11. The method according to claim 1 , further comprising: performing a first decryption function to generate a read threshold level decryption key stream, wherein each value in the read threshold level decryption key stream corresponds to at least one read memory cell; determining a read threshold for each read memory cell based at least on the corresponding threshold level decryption key stream; sensing voltage levels of a plurality of read memory cells; generating a cipher data bit stream by comparing the sensed voltage level for each of said read memory cells to the determined read thresholds for the respective memory cells; and performing a second decryption function on the cipher data bit stream to obtain an output data stream.
12. The method of claim 1 , wherein programming the cipher data bit stream into a memory comprises programming the cipher data bit stream into a first page of the memory based on a programming result of a second page of the memory, wherein the second page was programming using the wide incremental stepped pulse programming (ISPP).
13. A device comprising: a memory controller associated with a memory, the memory controller configured to:
perform a first encryption function on an input data stream to generate a cipher data bit stream, perform a second encryption function to generate a threshold level encryption key stream, wherein each value in the threshold level encryption key stream corresponds to at least one bit of the cipher data bit stream, and program the cipher data bit stream into the memory based on the corresponding values of the threshold level encryption key stream;
wherein the memory controller is configured to program the cipher data bit stream into the memory by programming the cipher data bit stream into the memory using an incremental stepped pulse programming (ISPP) step having a value based on the corresponding values of the threshold level encryption key stream.
14. The device of claim 13 , wherein the memory controller is further configured to program the cipher data bit stream into a memory based on the corresponding values of the threshold level encryption key stream by: determining a programming threshold for each bit in the cipher data bit stream based at least on the corresponding threshold level encryption key stream, and programming the cipher data bit stream into a memory using the determined programming thresholds corresponding thereto.
15. The device of claim 14 , wherein the number of possible values of the threshold level encryption key stream is greater than the number of possible values of the cipher data bit stream.
16. The device of claim 15 , wherein each value of the threshold level encryption key stream comprises two binary bits, and wherein the memory controller is configured to determine the programming threshold for each bit in the cipher data bit stream by selecting one of up to four programming threshold voltage levels based at least on the corresponding threshold level encryption key stream.
17. The device of claim 15 , wherein each value of the threshold level encryption key stream comprises three binary bits, and wherein the memory controller is configured to determine the programming threshold for each bit in the cipher data bit stream by selecting one of up to eight programming threshold voltage levels based at least on the corresponding threshold level encryption key stream.
18. The device of claim 15 , wherein each value of the threshold level encryption key stream comprises four binary bits, and wherein the memory controller is configured to determine the programming threshold for each bit in the cipher data bit stream by selecting one of up to sixteen programming threshold voltage levels based at least on the corresponding threshold level encryption key stream.
19. The device of claim 15 , wherein each value of the threshold level encryption key stream comprises five binary bits, and wherein the memory controller is configured to determine the programming threshold for each bit in the cipher data bit stream by selecting one of up to thirty two programming threshold voltage levels based at least on the corresponding threshold level encryption key stream.
20. The device of claim 14 , wherein the memory controller is configured to program the cipher data bit stream into the memory using the determined programming thresholds by simultaneously storing a page of cipher data bit stream values into a page of memory.
21. The device of claim 20 , the memory controller is configured to simultaneously program a plurality of cells in the page of memory with a corresponding value of the cipher data bit stream by: performing a coarse programming operation using a first incremental stepped pulse programming (ISPP) parameter, and if the voltage level of the cell after the coarse programming operation is between two desired voltage distribution lobes, then performing a fine programming operation to program the using a second ISPP parameter, wherein the first ISPP parameter is greater than the second ISPP parameter.
22. The device of claim 13 , wherein the memory controller is configured to program the cipher data bit stream into the memory based on the corresponding values of the threshold level encryption key stream by: for a bit of the cipher data bit stream having a logical 0 value, programming a corresponding memory cell to one of a first plurality of voltage levels, and for a bit of the cipher data bit stream having a logical 1value, programming a corresponding memory cell to one of a second plurality of voltage levels, wherein the first and second plurality of voltage levels are determined by the threshold level encryption key stream value corresponding to the bit of the cipher data bit stream.
23. The device according to claim 13 , wherein the memory controller is configured to: perform a first decryption function to generate a read threshold level decryption key stream, wherein each value in the read threshold level decryption key stream corresponds to at least one read memory cell, determine a read threshold for each read memory cell based at least on the corresponding threshold level decryption key stream, sense voltage levels of a plurality of read memory cells, generate a cipher data bit stream by comparing the sensed voltage level for each of said read memory cells to the determined read thresholds for the respective memory cells, and perform a second decryption function on the cipher data bit stream to obtain an output data stream.
24. The device of claim 13 , wherein the memory controller is configured to program the cipher data bit stream into the memory by programming the cipher data bit stream into a first page of the memory based on a programming result of a second page of the memory, wherein the second page was programming using the wide incremental stepped pulse programming (ISPP).