Continuous power transfer scheme for two-wire serial link
View Patent ↗The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.
1. A method of interfacing a first interface circuit with a second interface circuit having a tri-state buffer connected between a storage device and ground, the tri-state buffer including an input terminal to receive a first signal to be transmitted to the first interface circuit, an enable terminal, and an output terminal to transmit the first signal to the first interface circuit, the method comprising the steps of:
receiving a second signal having an AC-frequency component at the output terminal of the tri-state buffer, and
switching the tri-state buffer, such that (i) during a first time period, the tri-state buffer electrically transfers the second signal to a first terminal of the storage capacitor, and (ii) during a second time period different from the first time period, the tri-state buffer electrically transfers the second signal to ground rather than to the first terminal of the storage capacitor, wherein:
the steps of receiving and switching are performed during a first portion of a frame including the first and second time periods; and
the method further comprises inputting, during a second portion of the frame, the first signal to the input terminal of the tri-state buffer, such that the first signal is passed to the output terminal of the tri-state buffer during the second portion of the frame.
2. The method of claim 1 , wherein:
during the first time period the voltage of the second signal is above a first predetermined level; and
during the second time period the voltage of the second signal is below a second predetermined level.
3. The method of claim 2 , wherein: the first predetermined level is approximately the voltage at the storage device, and the second predetermined level is approximately the voltage at ground.
4. The method of claim 1 , wherein the tri-state buffer is switched in substantial synchronism with the second signal.
5. The method of claim 4 , wherein the step of switching comprises inputting at least a portion of the second signal to the input terminal of the tri-state buffer.
6. The method of claim 5 , wherein the steps of inputting the first signal and inputting the second signal to the input terminal of the tri-state buffer comprise the steps of:
inputting the first signal and the second signal to a mode selection switch; and
providing to the media selection switch a mode selection signal that causes the mode selection switch to select and output either the first signal or the second signal to the input terminal of the tri-state buffer.
7. The method of claim 1 , wherein the tri-state buffer rectifies the AC-frequency component of the second signal by (i) storing energy from the second signal in the storage capacitor during the first time period and (ii) preventing the second signal from dissipating energy stored in the storage capacitor through the tri-state buffer during the second time period.
8. An apparatus for interfacing a first interface circuit with a second interface circuit having a tri-state buffer connected between a storage device and ground, the tri-state buffer including an input terminal to receive a first signal to be transmitted to the first interface circuit, an enable terminal, and an output terminal to transmit the first signal to the first interface circuit, the apparatus comprising:
a means for receiving a second signal having an AC-frequency component at the output terminal of the tri-state buffer, and
a means for switching the tri-state buffer, such that (i) during a first time period, the tri-state buffer electrically transfers the second signal to a first terminal of the storage capacitor, and (ii) during a second time period different from the first time period, the tri-state buffer electrically transfers the second signal to ground rather than to the first terminal of the storage capacitor, wherein:
the means for receiving the second signal is configured to receive the second signal during a first portion of a frame including the first and second time periods;
the means for switching the tri-state buffer is configured to cause the tri-state buffer to transfer, during the first portion of the frame including the first and second time periods, the second signal (i) to the first terminal of the storage capacitor during the first time period and (ii) to ground during the second time period; and
the apparatus further comprises a means for inputting, during a second portion of the frame, the first signal to the input terminal of the tri-state buffer, such that the first signal is passed to the output terminal of the tri-state buffer during the second portion of the frame.
9. The apparatus of claim 8 , wherein the tri-state buffer is configured to rectify the AC-frequency component of the second signal by (i) storing energy from the second signal in the storage capacitor during the first time period and (ii) preventing the second signal from dissipating energy stored in the storage capacitor through the tri-state buffer during the second time period.