Method of manufacturing semiconductor device with multiple implantation steps

1. A method of manufacturing a semiconductor device comprising:

forming a first gate insulating film in a first region of a semiconductor substrate;

forming a second gate insulating film in a second region of the semiconductor substrate, the second gate insulating film being thinner than the first gate insulating film;

forming a third gate insulating film in a third region of the semiconductor substrate, the third gate insulating film being thinner than the first gate insulating film;

forming a first gate electrode, a second gate electrode, and a third gate electrode on the first gate insulating film, the second gate insulating film, and the third gate insulating film, respectively;

forming a first mask pattern after forming the first gate electrode, the second gate electrode, and the third gate electrode, the first mask pattern covering the second region while exposing the first region and the third region;

forming a first source drain extension in the semiconductor substrate beside the first gate electrode and forming a first pocket region in the semiconductor substrate beside the third gate electrode by implanting ions of a first impurity of a first conductivity type into the semiconductor substrate with the first mask pattern being used as a mask;

forming a second source drain extension in the semiconductor substrate beside the third gate electrode by implanting ions of a second impurity of a second conductivity type into the semiconductor substrate with the first mask pattern being used as a mask, under a condition that makes the second impurity under the first gate insulating film have a lower concentration than the first impurity;

forming a second mask pattern after removing the first mask pattern, the second mask pattern covering the first region and the third region while exposing the second region;

forming a second pocket region in the semiconductor substrate beside the second gate electrode by implanting ions of a third impurity of the first conductivity type into the semiconductor substrate with the second mask pattern being used as a mask, the third impurity having a smaller diffusion coefficient than the first impurity;

forming a third source drain extension in the semiconductor substrate beside the second gate electrode by implanting ions of a fourth impurity of the second conductivity type into the semiconductor substrate with the second mask pattern being used as a mask;

forming a first source drain region of the first conductivity type in the semiconductor substrate beside the first gate electrode;

forming a second source drain region of the second conductivity type in the semiconductor substrate beside the second gate electrode; and

forming a third source drain region of the second conductivity type in the semiconductor substrate beside the third gate electrode.

2. The method of manufacturing a semiconductor device according to the claim 1 , further comprising:

forming a thermal oxidation film on the first region, the second region, and the third region in the semiconductor substrate before forming the first gate insulating film, the second gate insulating film, and the third gate insulating film;

forming a third mask pattern on the thermal oxidation film, the third mask pattern covering the first region while exposing the second region and the third region; and

forming a first channel region in the second region and forming a second channel region in the third region by implanting ions of a fifth impurity of the first conductivity type in the second region and the third region of the semiconductor substrate with the third mask pattern being used as a mask.

3. The method of manufacturing a semiconductor device according to claim 1 , wherein the forming of the second source drain extension further includes:

implanting ions of a sixth impurity of the second conductivity type into a portion of the semiconductor substrate at a depth shallower than an implantation depth of the second impurity with the first mask pattern being used as a mask.

4. The method of manufacturing a semiconductor device according to claim 3 , wherein a diffusion coefficient of the sixth impurity is smaller than a diffusion coefficient of the second impurity.

5. The method of manufacturing a semiconductor device according to claim 4 , wherein

the second impurity is phosphorus, and

the sixth impurity is arsenic.

6. The method of manufacturing a semiconductor device according to claim 1 , wherein the third impurity is indium.

7. The method of manufacturing a semiconductor device according to claim 1 , wherein the forming of the first source drain extension and the first pocket region is performed by implanting the first impurity into the semiconductor substrate in a direction oblique to a normal direction of the semiconductor substrate.

8. The method of manufacturing a semiconductor device according to claim 1 , wherein the forming of the second source drain extension is performed under a state where the first gate insulating film is formed in the first region.

9. The method of manufacturing a semiconductor device according to claim 1 , wherein the forming of the second source drain extensions is performed by implanting ions of the second impurity into a portion of the semiconductor substrate at a depth shallower than the first pocket region.

10. The method of manufacturing a semiconductor device according to claim 1 , further comprising:

forming a fourth gate insulating film thinner than the first gate insulating film in a fourth region of the semiconductor substrate;

forming a fourth gate electrode on the fourth gate insulating film;

forming a third mask pattern covering the first region, the second region, and the third region, while exposing the fourth region;

forming a fourth source drain extension in the semiconductor substrate beside the fourth gate electrode by implanting ions of a seventh impurity of the first conductivity type into the semiconductor substrate with the third mask pattern being used as a mask, the seventh impurity having a larger diffusion coefficient than the third impurity; and

forming a fourth source drain region of the first conductivity type in the semiconductor substrate beside the fourth gate electrode.

11. The method of manufacturing a semiconductor device according to claim 10 , wherein the seventh impurity is boron.

12. The method of manufacturing a semiconductor device according to claim 1 , wherein the forming of the second source drain region and the forming of the third source drain region are performed as a single step.

13. The method of manufacturing a semiconductor device according to claim 1 , wherein the first conductivity type is a p type and the second conductivity type is an n type.

14. The method of manufacturing a semiconductor device according to claim 1 , wherein a gate length of the first gate electrode is longer than a gate length of the second gate electrode and the third gate electrode.