Semiconductor chip with seal ring and sacrificial corner pattern
View Patent ↗A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
1. A semiconductor device, comprising a low dielectric constant film having a relative dielectric constant less than 3.5, and a seal ring which is a moisture blocking wall forming a closed loop in a plan view,
wherein said seal ring includes a seal ring protrusion portion in inward protruding form in a vicinity of a corner of a chip,
wherein a passivation film covers said low dielectric constant film and the seal ring, and has a opening penetrating the passivation film, the opening formed in a vicinity of two chip end surfaces in a plan view, said two chip end surfaces forming the corner of the chip,
wherein a sacrifice pattern is provided outside of said seal ring protrusion portion of the seal ring from a center of a chip,
wherein the sacrifice pattern is a structure in wall-form for preventing progress of a crack,
wherein said passivation film is made of a SiN,
wherein said seal ring includes a Cu seal ring and Al seal ring formed above said Cu seal ring and said sacrifice pattern includes a Cu sacrifice pattern, and
wherein an Al sacrifice pattern is not formed above said sacrifice pattern.
2. The semiconductor device according to claim 1 ,
wherein said sacrifice pattern has a sacrifice pattern diagonal side which forms approximately a same angle with the two chip end surfaces that form said corner, and has a sacrifice pattern diagonal side that faces said corner.
3. The semiconductor device according to claim 1 , further comprising:
a number of low dielectric constant films that include said low dielectric constant film,
wherein said sacrifice pattern is configured to block a lowest layer from among said low dielectric constant films.
4. The semiconductor device according to claim 1 , further comprising:
a number of low dielectric constant films that include said low dielectric constant film, wherein
said sacrifice pattern is configured to block all of said number of low dielectric constant films.
5. The semiconductor device according to claim 1 ,
wherein said sacrifice pattern is configured to be separated from said seal ring in a plan view.
6. The semiconductor device according to claim 1 , comprising:
a sacrifice pattern group that includes a plurality of the sacrifice patterns.
7. The semiconductor device according to claim 6 ,
wherein the plurality of the sacrifice patterns included in said sacrifice pattern group respectively have a sacrifice pattern diagonal side which forms approximately a same angle with the two chip end surfaces that form said corner and faces said corner.
8. The semiconductor device according to claim 7 ,
wherein at least some of said plurality of the sacrifice patterns are arranged so that sacrifice patterns that are closer to the center of the chip have a longer sacrifice pattern diagonal side.